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authorJonathan A. Kollasch <jakllsch@kollasch.net>2011-08-01 14:24:02 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-08-04 17:28:36 +0200
commit0df0e14fb5b613e76ff022359c55d5df5633b40f (patch)
treed2ba6734d1ee6220a7d7b55d66c109fbc79a8718 /src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
parente089a3f68ddbbaaceb25d00322b3e7ccc27a48a8 (diff)
Add voltage control of southbridge and RAM on ms7135
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl')
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