diff options
author | efdesign98 <efdesign98@gmail.com> | 2011-08-04 12:09:17 -0600 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-08-06 18:06:18 +0200 |
commit | 84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch) | |
tree | 57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1 | |
parent | 0df0e14fb5b613e76ff022359c55d5df5633b40f (diff) |
Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus. It also fixes (again) a ton of warnings, although
not all of them are gone. The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.
Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1')
3 files changed, 139 insertions, 14 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 0a0828ee32..453576d623 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -59,6 +59,7 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "GnbGfxFamServices.h" +#include "GfxEnumConnectors.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE @@ -104,6 +105,17 @@ typedef struct { *---------------------------------------------------------------------------------------- */ +EXT_CONNECTOR_INFO* +GfxIntegratedExtConnectorInfo ( + IN UINT8 ConnectorType + ); + +EXT_DISPLAY_DEVICE_INFO* +GfxIntegratedExtDisplayDeviceInfo ( + IN UINT8 DisplayDeviceEnum, + IN UINT8 DisplayDeviceIndex + ); + AGESA_STATUS GfxIntegratedEnumConnectorsForDevice ( IN UINT8 DisplayDeviceEnum, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index e42a83f675..feb612305f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -91,12 +91,81 @@ typedef struct { BOOLEAN Valid; ///< State valid UINT32 Sclk; ///< Sclk in kHz UINT8 Vid; ///< VID index + UINT16 Tdp; ///< Tdp limit } DPM_STATE; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +SW_STATE* +GfxPowerPlayCreateSwState ( + IN OUT SW_STATE *SwStateArray + ); + +UINT8 +GfxPowerPlayCreateDpmState ( + IN DPM_STATE *DpmStateArray, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ); + +UINT8 +GfxPowerPlayAddDpmState ( + IN DPM_STATE *DpmStateArray, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ); + +VOID +GfxPowerPlayAddDpmStateToSwState ( + IN OUT SW_STATE *SwStateArray, + IN UINT8 DpmStateIndex + ); + +UINT32 +GfxPowerPlayCopyStateInfo ( + IN OUT STATE_ARRAY *StateArray, + IN SW_STATE *SwStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxPowerPlayCopyClockInfo ( + IN CLOCK_INFO_ARRAY *ClockInfoArray, + IN DPM_STATE *DpmStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxPowerPlayCopyNonClockInfo ( + IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray, + IN SW_STATE *SwStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxPowerPlayIsFusedStateValid ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +UINT16 +GfxPowerPlayGetClassificationFromFuses ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ); VOID GfxIntegratedDebugDumpPpTable ( @@ -106,6 +175,45 @@ GfxIntegratedDebugDumpPpTable ( /*----------------------------------------------------------------------------------------*/ /** + * Locate existing tdp + * + * + * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY + * @param[in] Sclk Sclk in 10kHz + * @param[in] StdHeader Standard configuration header + * @retval Tdp limit in DPM state array + */ + +UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + UINT32 DpmIndex; + UINT32 DpmSclk; + UINT32 DeltaSclk; + UINT32 MinDeltaSclk; + + DpmIndex = 0; + MinDeltaSclk = 0xFFFFFFFF; + for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { + if (PpFuses->SclkDpmDid[Index] != 0) { + DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); + DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); + if (DeltaSclk < MinDeltaSclk) { + MinDeltaSclk = MinDeltaSclk; + DpmIndex = Index; + } + } + } + return PpFuses->SclkDpmTdpLimit[DpmIndex]; +} + +/*----------------------------------------------------------------------------------------*/ +/** * Create new software state * * @@ -136,6 +244,7 @@ GfxPowerPlayCreateSwState ( * @param[in, out] DpmStateArray Pointer to DPM state array * @param[in] Sclk SCLK in kHz * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit * @retval Index of state entry in DPM state array */ @@ -143,7 +252,8 @@ UINT8 GfxPowerPlayCreateDpmState ( IN DPM_STATE *DpmStateArray, IN UINT32 Sclk, - IN UINT8 Vid + IN UINT8 Vid, + IN UINT16 Tdp ) { UINT8 Index; @@ -152,6 +262,7 @@ GfxPowerPlayCreateDpmState ( DpmStateArray[Index].Sclk = Sclk; DpmStateArray[Index].Vid = Vid; DpmStateArray[Index].Valid = TRUE; + DpmStateArray[Index].Tdp = Tdp; return Index; } } @@ -166,6 +277,7 @@ GfxPowerPlayCreateDpmState ( * @param[in, out] DpmStateArray Pointer to DPM state array * @param[in] Sclk SCLK in kHz * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit * @retval Index of state entry in DPM state array */ @@ -173,7 +285,8 @@ UINT8 GfxPowerPlayAddDpmState ( IN DPM_STATE *DpmStateArray, IN UINT32 Sclk, - IN UINT8 Vid + IN UINT8 Vid, + IN UINT16 Tdp ) { UINT8 Index; @@ -182,7 +295,7 @@ GfxPowerPlayAddDpmState ( return Index; } } - return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid); + return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp); } /*----------------------------------------------------------------------------------------*/ @@ -250,7 +363,6 @@ GfxPowerPlayCopyStateInfo ( * @param[in] DpmStateArray Pointer to DPM state array * @param[in] StdHeader Standard configuration header */ - UINT32 GfxPowerPlayCopyClockInfo ( IN CLOCK_INFO_ARRAY *ClockInfoArray, @@ -266,6 +378,7 @@ GfxPowerPlayCopyClockInfo ( ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (DpmStateArray[Index].Sclk >> 16); ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (DpmStateArray[Index].Sclk); ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = DpmStateArray[Index].Vid; + ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = DpmStateArray[Index].Tdp; ClkStateIndex++; } } @@ -346,7 +459,6 @@ GfxPowerPlayIsFusedStateValid ( * @param[in] Gfx Gfx configuration info * @retval State classification */ - UINT16 GfxPowerPlayGetClassificationFromFuses ( IN UINT8 Index, @@ -416,6 +528,7 @@ GfxPowerPlayBuildTable ( UINT32 NonClockArrayLength; SW_STATE *State; PP_FUSE_ARRAY *PpFuses; + UINT32 Sclk; PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); ASSERT (PpFuses != NULL); @@ -446,10 +559,9 @@ GfxPowerPlayBuildTable ( } for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) { if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) { - UINT32 Sclk; Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (Gfx)) : 0; if (Sclk != 0) { - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex]); + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); } } @@ -459,13 +571,15 @@ GfxPowerPlayBuildTable ( // Create Boot State State = GfxPowerPlayCreateSwState (SwStateArray); State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0); + Sclk = 200 * 100; + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); // Create Thermal State State = GfxPowerPlayCreateSwState (SwStateArray); State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0); + Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (Gfx)); + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); //Copy state info to actual PP table @@ -562,11 +676,11 @@ GfxIntegratedDebugDumpPpTable ( IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16) ); - IDS_HDT_CONSOLE (GFX_MISC, " Cac = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].leakage - ); IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", ClockInfoArrayPtr->ClockInfo[Index].vddcIndex ); + IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].tdpLimit + ); } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h index 6fe93d7298..7aea7dc865 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h @@ -106,8 +106,7 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) UCHAR vddcIndex; ///< 2-bit VDDC index; - UCHAR leakage; ///< Absolute Cac value; - UCHAR rsv; ///< Reserved + USHORT tdpLimit; ///< TDP Limit USHORT rsv1; ///< Reserved ULONG rsv2[2]; ///< Reserved } ATOM_PPLIB_SUMO_CLOCK_INFO; |