Update AMD F14 Agesa to support Rev C0 cpus

This change updates the AMD Agesa code to support the Family 14 rev C0 cpus. It also fixes (again) a ton of warnings, although not all of them are gone. The warning fixes affect code in the Family 12 tree as well, so there are some small changes therein. This code has been tested on a Persimmon and passes Abuild. This is the first (and largest) of a number of commits to complete the upgrade. Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/131 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
author: efdesign98 <efdesign98@gmail.com> 2011-08-04 12:09:17 -0600
committer: Patrick Georgi <patrick@georgi-clan.de> 2011-08-06 18:06:18 +0200
commit: 84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch)
tree: 57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/CPU/Family
parent: 0df0e14fb5b613e76ff022359c55d5df5633b40f (diff)
48 files changed, 5124 insertions, 574 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c
index d6b1443ff0..4905e77aeb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c
@@ -108,19 +108,19 @@ F10InitializeIoCstate (
   IN       AMD_CONFIG_PARAMS         *StdHeader
   )
 {
-  UINT64   MsrRegister;
+  UINT64   MsrReg;
   AP_TASK  TaskPtr;
 
   if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
     // Initialize MSRC001_0073[CstateAddr] on each core to a region of
     // the IO address map with 8 consecutive available addresses.
-    MsrRegister = 0;
+    MsrReg = 0;
 
-    ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
+    ((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
 
     TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
     TaskPtr.DataTransfer.DataSizeInDwords = 2;
-    TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+    TaskPtr.DataTransfer.DataPtr = &MsrReg;
     TaskPtr.DataTransfer.DataTransferFlags = 0;
     TaskPtr.ExeFlags = WAIT_FOR_CORE;
     ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
@@ -264,7 +264,7 @@ F10IsIoCstateFeatureSupported (
   IN       AMD_CONFIG_PARAMS         *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   CPUID_DATA     CpuId;
   CPU_LOGICAL_ID LogicalId;
 
@@ -274,8 +274,8 @@ F10IsIoCstateFeatureSupported (
   if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
     LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
     if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
-      LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrRegister, StdHeader);
-      if ((MsrRegister & 0xffffffff) >= 0x010000BF) {
+      LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrReg, StdHeader);
+      if ((MsrReg & 0xffffffff) >= 0x010000BF) {
         return TRUE;
       }
     }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
index 9b99f15f72..badc725c86 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -250,16 +250,16 @@ PmNbCofVidInitP0P1Core (
   )
 {
   UINT32 MsrAddress;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-  MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
-  LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
-  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
-  ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
-  LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+  MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrReg)->StartupPstate) + PS_REG_BASE);
+  LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrReg, StdHeader);
+  ((PSTATE_MSR *) &MsrReg)->NbVid = *(UINT8 *) NewNbVid;
+  LibAmdMsrWrite (PS_REG_BASE, &MsrReg, StdHeader);
   FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
 }
 
@@ -283,16 +283,16 @@ PmNbCofVidInitWarmCore (
   )
 {
   UINT32 MsrAddress;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
   for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
-    LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &MsrRegister)->IddValue != 0) {
-      if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
-        ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
-        LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+    LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
+    if (((PSTATE_MSR *) &MsrReg)->IddValue != 0) {
+      if ((((PSTATE_MSR *) &MsrReg)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
+        ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
+        LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader);
       }
     }
   }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
index f69436f60b..fd40297aed 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -174,14 +174,14 @@ PmNbPstateInitCore (
   )
 {
   UINT32 MsrAddress;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
-    LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
-      ((PSTATE_MSR *) &MsrRegister)->NbDid = 1;
-      ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
-      LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+    LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
+    if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
+      ((PSTATE_MSR *) &MsrReg)->NbDid = 1;
+      ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
+      LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader);
     }
   }
 }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
index d92bf99026..3c3fa89463 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -134,18 +134,18 @@ F10InitializeHwC1e (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   AP_TASK TaskPtr;
 
-  MsrRegister = 0;
-  ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData;
-  ((INTPEND_MSR *) &MsrRegister)->IoRd = 1;
-  ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1;
-  ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
+  MsrReg = 0;
+  ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData;
+  ((INTPEND_MSR *) &MsrReg)->IoRd = 1;
+  ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 1;
+  ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0;
 
   TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
   TaskPtr.DataTransfer.DataSizeInDwords = 2;
-  TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+  TaskPtr.DataTransfer.DataPtr = &MsrReg;
   TaskPtr.DataTransfer.DataTransferFlags = 0;
   TaskPtr.ExeFlags = WAIT_FOR_CORE;
   ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
@@ -168,16 +168,16 @@ F10InitializeHwC1eOnCore (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64  MsrRegister;
+  UINT64  MsrReg;
 
   // Enable C1e
   LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
 
   // Set OS Visible Workaround Status BIT1 to indicate that C1e
   // is enabled.
-  LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
-  MsrRegister |= BIT1;
-  LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
+  LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader);
+  MsrReg |= BIT1;
+  LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader);
 }
 
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
index 45a1aacfe4..64fa687207 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
@@ -126,19 +126,19 @@ F10InitializeSwC1e (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   AP_TASK TaskPtr;
 
-  MsrRegister = 0;
-  ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
-  ((INTPEND_MSR *) &MsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
-  ((INTPEND_MSR *) &MsrRegister)->IoRd = 0;
-  ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
-  ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 1;
+  MsrReg = 0;
+  ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
+  ((INTPEND_MSR *) &MsrReg)->IoMsgData = PlatformConfig->C1ePlatformData2;
+  ((INTPEND_MSR *) &MsrReg)->IoRd = 0;
+  ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0;
+  ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 1;
 
   TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
   TaskPtr.DataTransfer.DataSizeInDwords = 2;
-  TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+  TaskPtr.DataTransfer.DataPtr = &MsrReg;
   TaskPtr.DataTransfer.DataTransferFlags = 0;
   TaskPtr.ExeFlags = WAIT_FOR_CORE;
   ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
@@ -161,16 +161,16 @@ F10InitializeSwC1eOnCore (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64  MsrRegister;
+  UINT64  MsrReg;
 
   // Enable C1e
   LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
 
   // Set OS Visible Workaround Status BIT1 to indicate that C1e
   // is enabled.
-  LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
-  MsrRegister |= BIT1;
-  LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
+  LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader);
+  MsrReg |= BIT1;
+  LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader);
 }
 
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
index c422955712..9910fd9a71 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -320,7 +320,7 @@ F10CommonRevCGetNbPstateInfo (
   UINT32   NbVid;
   UINT32   PciRegister;
   UINT32   ProductInfoRegister;
-  UINT64   MsrRegister;
+  UINT64   MsrReg;
   BOOLEAN  PstateIsValid;
 
   PstateIsValid = TRUE;
@@ -339,8 +339,8 @@ F10CommonRevCGetNbPstateInfo (
       PciAddress->Address.Register = CPTC0_REG;
       LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
       NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
-      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-      NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid;
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+      NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid;
     } else {
       NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
       NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
index 33f7e040a5..ec7b09be6d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
@@ -324,11 +324,11 @@ F10HookDisableCache (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64  MsrRegister;
+  UINT64  MsrReg;
 
-  LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader);
-  MsrRegister |= BIT42;
-  LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader);
+  LibAmdMsrRead (MSR_BU_CFG2, &MsrReg, StdHeader);
+  MsrReg |= BIT42;
+  LibAmdMsrWrite (MSR_BU_CFG2, &MsrReg, StdHeader);
 }
 
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
index 54e0d5fd83..80be0777f0 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -225,22 +225,22 @@ F10InitializeMsgBasedC1eOnCore (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
-  LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader);
-  ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
-  ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
-  ((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1;
-  ((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0;
-  ((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0;
-  ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
-  LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader);
+  LibAmdMsrRead (MSR_INTPEND, &MsrReg, StdHeader);
+  ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0;
+  ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0;
+  ((INTPEND_MSR *) &MsrReg)->BmStsClrOnHltEn = 1;
+  ((INTPEND_MSR *) &MsrReg)->IntrPndMsgDis = 0;
+  ((INTPEND_MSR *) &MsrReg)->IntrPndMsg = 0;
+  ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
+  LibAmdMsrWrite (MSR_INTPEND, &MsrReg, StdHeader);
 
   // Set MSRC001_0015[HltXSpCycEn] = 1
-  LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader);
-  MsrRegister |= BIT12;
-  LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader);
+  LibAmdMsrRead (MSR_HWCR, &MsrReg, StdHeader);
+  MsrReg |= BIT12;
+  LibAmdMsrWrite (MSR_HWCR, &MsrReg, StdHeader);
 }
 
 /*---------------------------------------------------------------------------------------*/
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
index 1d46de6e3a..3a4d127c0c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -309,7 +309,7 @@ F10CommonRevDGetNbPstateInfo (
   )
 {
   UINT32   PciRegister;
-  UINT64   MsrRegister;
+  UINT64   MsrReg;
   BOOLEAN  PstateIsValid;
 
   PstateIsValid = FALSE;
@@ -319,8 +319,8 @@ F10CommonRevDGetNbPstateInfo (
     LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
     *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
     *FreqDivisor = 1;
-    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-    *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+    *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid)));
     PstateIsValid = TRUE;
   }
   return PstateIsValid;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
index 82a52e3495..53904122af 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
@@ -87,12 +87,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
       AMD_FAMILY_10,                      // CpuFamily
       AMD_F10_GT_B0                       // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MSR_LS_CFG,                           // MSR Address
       0x0000000000000000,                   // OR Mask
       (1 << 1)                              // NAND Mask
-    }
+    }}
   },
 
 // MSR_BU_CFG (0xC0011023)
@@ -103,12 +103,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
       AMD_FAMILY_10,                      // CpuFamily
       AMD_F10_GT_B0                       // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MSR_BU_CFG,                           // MSR Address
       (1 << 21),                            // OR Mask
       (1 << 21),                            // NAND Mask
-    }
+    }}
   },
 
 // MSR_BU_CFG2 (0xC001102A)
@@ -120,12 +120,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
       AMD_FAMILY_10,                      // CpuFamily
       AMD_F10_GT_C0                       // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MSR_BU_CFG2,                          // MSR Address
       0x0004000000000000,                   // OR Mask
       0x0004000000000000,                   // NAND Mask
-    }
+    }}
   }
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
index 635c424131..7a080d548a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
@@ -285,7 +285,7 @@ F10CommonRevEGetNbPstateInfo (
   )
 {
   UINT32   PciRegister;
-  UINT64   MsrRegister;
+  UINT64   MsrReg;
   BOOLEAN  PstateIsValid;
 
   PstateIsValid = FALSE;
@@ -295,8 +295,8 @@ F10CommonRevEGetNbPstateInfo (
     LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
     *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
     *FreqDivisor = 1;
-    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-    *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+    *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid)));
     PstateIsValid = TRUE;
   }
   return PstateIsValid;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
index b2df819e0a..79a922e51c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -122,7 +122,7 @@ DmiF10GetInfo (
   CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
   CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
 
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
   CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
   CpuInfoPtr->TotalCoreNumber--;
 
@@ -239,7 +239,7 @@ DmiF10GetMaxSpeed (
   PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
 
   FamilyServices = NULL;
-  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
   ASSERT (FamilyServices != NULL);
   NumBoostStates = 0;
   LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
index 671af0e94c..d9639c228f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -165,7 +165,7 @@ F10PmAfterReset (
   UINT32    Core;
   UINT32    AndMask;
   UINT32    OrMask;
-  UINT64    MsrRegister;
+  UINT64    MsrReg;
   PCI_ADDR  PciAddress;
   AP_TASK   TaskPtr;
   AGESA_STATUS IgnoredSts;
@@ -179,8 +179,8 @@ F10PmAfterReset (
   // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance
   //        P-state supported, as indicated in MSRC001_00[68:64][PstateEn]
   for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {
-    LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+    LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+    if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
       break;
     }
   }
@@ -227,7 +227,7 @@ F10PmAfterResetCore (
   UINT32 Ignored;
   UINT32 PsMaxVal;
   UINT32 PciRegister;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   UINT64 SavedMsr;
   UINT64 CurrentLimitMsr;
   PCI_ADDR PciAddress;
@@ -238,13 +238,13 @@ F10PmAfterResetCore (
 
   // Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
   GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-  GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
+  GetCpuServicesFromLogicalId (&LogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
   if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
-    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-    if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
-      LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
-      MsrRegister |= BIT62;
-      LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+    if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
+      LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+      MsrReg |= BIT62;
+      LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
     }
   }
 
@@ -254,8 +254,8 @@ F10PmAfterResetCore (
   PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
 
   // Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
-  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-  if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate !=
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+  if (((COFVID_STS_MSR *) &MsrReg)->CurPstate !=
       ((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
     GoToStep = STEP20;
   } else {
@@ -282,8 +282,8 @@ F10PmAfterResetCore (
 
     // Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
     //        register pointed to by F3xDC[PstateMaxVal]+1
-    LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader);
-    LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+    LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrReg, StdHeader);
+    LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrReg, StdHeader);
 
     // Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
     IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
@@ -310,11 +310,11 @@ F10PmAfterResetCore (
 
     // Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
     if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
-      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
-        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
-        MsrRegister |= BIT62;
-        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) {
+        LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+        MsrReg |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
       }
     }
 
@@ -343,11 +343,11 @@ F10PmAfterResetCore (
 
     // Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
     if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
-      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
-        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
-        MsrRegister |= BIT62;
-        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
+        LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+        MsrReg |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
       }
     }
 
@@ -363,11 +363,11 @@ F10PmAfterResetCore (
     // Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
     //         the sequence
     if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
-      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
-        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
-        MsrRegister |= BIT62;
-        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) {
+        LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+        MsrReg |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
         break;
       }
     }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
index 031a9a4d62..877a12260c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -168,7 +168,7 @@ F10PmPwrCheck (
   UINT32      OrMask;
   UINT32      PstateLimit;
   PCI_ADDR    PciAddress;
-  UINT64      MsrRegister;
+  UINT64      MsrReg;
   AP_TASK     TaskPtr;
   CPUID_DATA  CpuidData;
   AGESA_STATUS IgnoredSts;
@@ -182,8 +182,8 @@ F10PmPwrCheck (
 
   // get the Max P-state value
   for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
-    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrReg, StdHeader);
+    if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
       break;
     }
   }
@@ -331,17 +331,17 @@ F10PmPwrCheckCore (
   UINT8  DisPsNum;
   UINT8  CurrentPs;
   UINT8  EnBsNum;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
   PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
   DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
              ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
   EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates;
 
-  LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
-  CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
+  LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
+  CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrReg)->CurPstate);
 
   if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
 
@@ -413,9 +413,9 @@ F10PmPwrChkCopyPstate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
-  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
-  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
+  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrReg, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrReg, StdHeader);
 }
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
index 4011971498..6f6c2d0b12 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
@@ -183,7 +183,7 @@ F10CpuAmdPmPwrPlaneInit (
   UINT32    AndMask;
   UINT32    OrMask;
   UINT32    ProcessorPackageType;
-  UINT64    MsrRegister;
+  UINT64    MsrReg;
   AP_TASK   TaskPtr;
   AGESA_STATUS  IgnoredSts;
   PLATFORM_FEATS Features;
@@ -266,10 +266,10 @@ F10CpuAmdPmPwrPlaneInit (
     OrMask = 0x00000000;
     ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
     ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
-    LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
-    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
-    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
-    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
+    LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrReg, StdHeader);
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuFid;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuDid;
     PciAddress.Address.Register = POPUP_PSTATE_REG;
     ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
 
@@ -278,7 +278,7 @@ F10CpuAmdPmPwrPlaneInit (
     AndMask = 0xFFFFFFFF;
     ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
     OrMask = 0x00000000;
-    ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
+    ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid;
     ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
 
     // Set up Altvid slam time
@@ -323,20 +323,20 @@ F10PmPwrPlaneInitPviCore (
   UINT32 MsrAddr;
   UINT32 NbVid;
   UINT32 CpuVid;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) {
-    LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) {
-      NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid);
-      CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+    LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+    if (((PSTATE_MSR *) &MsrReg)->PsEnable == (UINT64) 1) {
+      NbVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->NbVid);
+      CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
       if (NbVid != CpuVid) {
         if (NbVid > CpuVid) {
           NbVid = CpuVid;
         }
-        ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid;
-        ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid;
-        LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader);
+        ((PSTATE_MSR *) &MsrReg)->NbVid = NbVid;
+        ((PSTATE_MSR *) &MsrReg)->CpuVid = NbVid;
+        LibAmdMsrWrite (MsrAddr, &MsrReg, StdHeader);
       }
     }
   }
@@ -375,7 +375,7 @@ F10CalculateAltvidVSSlamTimeOnCore (
   UINT8     PminVidCode;
   UINT32    MsrAddr;
   UINT32    PciRegister;
-  UINT64    MsrRegister;
+  UINT64    MsrReg;
   PCI_ADDR  LocalPciAddress;
 
   // Calculate Slam Time
@@ -384,17 +384,17 @@ F10CalculateAltvidVSSlamTimeOnCore (
   //   decimals.
 
   // Get Pmin's index
-  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
-  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader);
+  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE);
 
   // Get Pmin's VID
-  LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
-  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+  LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
 
   // If SVI, we only care about CPU VID.
   // If PVI, determine the higher voltage b/t NB and CPU
   if (PviModeFlag) {
-    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
     if (PminVidCode > NbVid) {
       PminVidCode = NbVid;
     }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
index ed476a166d..8a2a381510 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -308,13 +308,13 @@ F10GetPstateFrequency (
   UINT8 TempValue;
   UINT32 CpuDid;
   UINT32 CpuFid;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   ASSERT (StateNumber < NM_PS_REG);
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
-  CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid);
-  CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+  CpuDid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDid);
+  CpuFid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuFid);
 
   switch (CpuDid) {
   case 0:
@@ -380,7 +380,7 @@ F10PstateLevelingCoreMsrModify (
   PCI_ADDR           PciAddress;
   CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
 
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
   ASSERT (FamilySpecificServices != NULL);
 
   Ignored = 0;
@@ -521,15 +521,15 @@ F10GetPstatePower (
   UINT32  Power;
   PCI_ADDR PciAddress;
   UINT32  TempVar_a;
-  UINT64  MsrRegister;
+  UINT64  MsrReg;
   AGESA_STATUS IgnoredSts;
 
   ASSERT (StateNumber < NM_PS_REG);
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
-  CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
-  IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
-  IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+  CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
+  IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue);
+  IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv);
 
   IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
   GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
@@ -654,7 +654,7 @@ F10GetPstateRegisterInfo (
   IN       AMD_CONFIG_PARAMS   *StdHeader
   )
 {
-  UINT64               MsrRegister;
+  UINT64               MsrReg;
   UINT32               PciRegister;
   PCI_ADDR             PciAddress;
   CPUID_DATA           CpuidData;
@@ -672,9 +672,9 @@ F10GetPstateRegisterInfo (
   *SwPstateNumber = PState;
 
   // Read PSTATE MSRs
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrReg, StdHeader);
 
-  if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+  if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
     // PState enable = bit 63
     *PStateEnabled = TRUE;
     // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
@@ -688,9 +688,9 @@ F10GetPstateRegisterInfo (
   }
 
   // Bits 39:32 (high 32 bits [7:0])
-  *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
+  *IddVal = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddValue;
   // Bits 41:40 (high 32 bits [9:8])
-  *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
+  *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddDiv;
 
   return (AGESA_SUCCESS);
 }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
index df6e58b3a4..d07084a060 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -119,7 +119,7 @@ F10PmSwVoltageTransition (
   UINT32    Socket;
   UINT32    Module;
   UINT32    Ignored;
-  UINT64    MsrRegister;
+  UINT64    MsrReg;
   PCI_ADDR  PciAddress;
   AGESA_STATUS IgnoredSts;
 
@@ -130,9 +130,9 @@ F10PmSwVoltageTransition (
   PciAddress.Address.Register = PW_CTL_MISC_REG;
   LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
   if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) {
-    LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
-    ((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode;
-    LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+    LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader);
+    ((COFVID_CTRL_MSR *) &MsrReg)->CpuVid = VidCode;
+    LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader);
     F10WaitOutVoltageTransition  (TRUE, StdHeader);
   } else
     return;
@@ -270,22 +270,22 @@ F10SwVoltageTransitionServerNbCore (
   )
 {
   UINT32 VidCode;
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) {
     VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode;
   } else {
-    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-    VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid);
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+    VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrReg)->CurNbVid);
     if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
       --VidCode;
     } else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
       ++VidCode;
     }
   }
-  LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
-  ((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode;
-  LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+  LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader);
+  ((COFVID_CTRL_MSR *) &MsrReg)->NbVid = VidCode;
+  LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader);
 
   if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
     return 0;
@@ -323,7 +323,7 @@ F10ProgramVSSlamTimeOnSocket (
   UINT32   MsrAddr;
   UINT32   OrMask;
   UINT32   PciRegister;
-  UINT64   MsrRegister;
+  UINT64   MsrReg;
   BOOLEAN  IsPviMode;
   PCI_ADDR LocalPciAddress;
 
@@ -339,30 +339,30 @@ F10ProgramVSSlamTimeOnSocket (
   }
 
   // Get P0's voltage
-  LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader);
-  P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+  LibAmdMsrRead (PS_REG_BASE, &MsrReg, StdHeader);
+  P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
 
   // If SVI, we only care about CPU VID.
   // If PVI, determine the higher voltage between NB and CPU
   if (IsPviMode) {
-    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
     if (P0VidCode > NbVid) {
       P0VidCode = NbVid;
     }
   }
 
   // Get Pmin's index
-  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
-  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader);
+  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE);
 
   // Get Pmin's VID
-  LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
-  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+  LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
 
   // If SVI, we only care about CPU VID.
   // If PVI, determine the higher voltage b/t NB and CPU
   if (IsPviMode) {
-    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
     if (PminVidCode > NbVid) {
       PminVidCode = NbVid;
     }
@@ -459,12 +459,12 @@ F10DisablePstate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   ASSERT (StateNumber < NM_PS_REG);
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
-  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ((PSTATE_MSR *) &MsrReg)->PsEnable = 0;
+  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
   return (AGESA_SUCCESS);
 }
 
@@ -489,18 +489,18 @@ F10TransitionPstate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   ASSERT (StateNumber < NM_PS_REG);
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
-  LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
-  ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
-  LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+  LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader);
+  ((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader);
   if (WaitForTransition) {
     do {
-      LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
-    } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
+      LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
+    } while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber);
   }
   return (AGESA_SUCCESS);
 }
@@ -525,15 +525,15 @@ F10GetTscRate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
 
   FamilyServices = NULL;
-  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
   ASSERT (FamilyServices != NULL);
 
-  LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
-  if ((MsrRegister & 0x01000000) != 0) {
+  LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader);
+  if ((MsrReg & 0x01000000) != 0) {
     return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
   } else {
     return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
@@ -564,7 +564,7 @@ F10GetCurrentNbFrequency (
   UINT32  Core;
   UINT32  NbFid;
   UINT32  PciRegister;
-  UINT64  MsrRegister;
+  UINT64  MsrReg;
   PCI_ADDR PciAddress;
   AGESA_STATUS ReturnCode;
 
@@ -577,8 +577,8 @@ F10GetCurrentNbFrequency (
       PciAddress.Address.Register = CPTC0_REG;
       LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
       NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
-      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
-      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
         *FrequencyInMHz = ((NbFid + 4) * 200);
       } else {
         *FrequencyInMHz = (((NbFid + 4) * 200) / 2);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
index 48823ec080..2b7be5dcad 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
@@ -144,12 +144,12 @@ F14InitializeC6 (
   UINT32   i;
   UINT32   MaxEnabledPstate;
   UINT32   PciRegister;
-  UINT64   MsrRegister;
+  UINT64   MsrReg;
   PCI_ADDR PciAddress;
 
   for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
-    LibAmdMsrRead (i, &MsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+    LibAmdMsrRead (i, &MsrReg, StdHeader);
+    if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
       break;
     }
   }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
index 43f0c68bbb..c2536eda0d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
@@ -115,28 +115,28 @@ F14InitializeIoCstate (
   UINT32   i;
   UINT32   MaxEnabledPstate;
   UINT32   PciRegister;
-  UINT64   MsrRegister;
+  UINT64   MsrReg;
   AP_TASK  TaskPtr;
   PCI_ADDR PciAddress;
 
   if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
     for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
-      LibAmdMsrRead (i, &MsrRegister, StdHeader);
-      if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      LibAmdMsrRead (i, &MsrReg, StdHeader);
+      if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
         break;
       }
     }
     MaxEnabledPstate = i - MSR_PSTATE_0;
     // Initialize MSRC001_0073[CstateAddr] on each core to a region of
     // the IO address map with 8 consecutive available addresses.
-    MsrRegister = 0;
-    ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
-    ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) &&
-            (((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8));
+    MsrReg = 0;
+    ((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
+    ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr != 0) &&
+            (((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr <= 0xFFF8));
 
     TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
     TaskPtr.DataTransfer.DataSizeInDwords = 2;
-    TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+    TaskPtr.DataTransfer.DataPtr = &MsrReg;
     TaskPtr.DataTransfer.DataTransferFlags = 0;
     TaskPtr.ExeFlags = WAIT_FOR_CORE;
     ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
index 1b1c6fb03b..37203f3a8b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
@@ -63,7 +63,7 @@
 
 // Patch code 0500000B for 5000 and equivalent
 CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B =
-{
+{{
 0x10,
 0x20,
 0x01,
@@ -1632,7 +1632,7 @@ CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B =
 0xe9,
 0xb2,
 0x6d
-};
+}};
 
 /*----------------------------------------------------------------------------------------
  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
index 5bde1d9ff5..a6dbf48913 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
@@ -63,7 +63,7 @@
 
 // Patch code 0500001A for 5001 and equivalent
 CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A =
-{
+{{
 0x10,
 0x20,
 0x08,
@@ -1632,7 +1632,7 @@ CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A =
 0x73,
 0x52,
 0x3b
-};
+}};
 
 /*----------------------------------------------------------------------------------------
  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c
new file mode 100644
index 0000000000..bdc8abd2a9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c
@@ -0,0 +1,1900 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Microcode patch.
+ *
+ * Fam14 Microcode Patch rev 05000028 for 5010 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x14
+ * @e \$Revision: 37850 $   @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 05000028 for 5010 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000028 =
+{{
+0x10,
+0x20,
+0x24,
+0x11,
+0x28,
+0x00,
+0x00,
+0x05,
+0x01,
+0x80,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x10,
+0x50,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x89,
+0x66,
+0x9f,
+0x9a,
+0x14,
+0x8a,
+0xcd,
+0xbb,
+0x71,
+0x6b,
+0x59,
+0xe0,
+0xf1,
+0xec,
+0x1d,
+0xe2,
+0xa1,
+0xcb,
+0xdd,
+0x85,
+0xd4,
+0x54,
+0x18,
+0x05,
+0x1f,
+0x71,
+0x70,
+0x1f,
+0xb5,
+0x6b,
+0x86,
+0xa2,
+0x37,
+0x5e,
+0x14,
+0x1b,
+0xdd,
+0xf4,
+0x40,
+0x31,
+0x90,
+0x8a,
+0xa3,
+0xc1,
+0x4a,
+0x5c,
+0xb8,
+0x36,
+0xf1,
+0xe8,
+0x7e,
+0x4c,
+0x2d,
+0xc0,
+0x51,
+0x92,
+0xd8,
+0xb4,
+0x9d,
+0x6c,
+0xa6,
+0xd1,
+0x3b,
+0x6c,
+0xed,
+0x8e,
+0x4a,
+0x2e,
+0xf4,
+0x33,
+0xbe,
+0xcf,
+0x57,
+0xf9,
+0xa2,
+0x24,
+0x28,
+0x81,
+0x63,
+0x04,
+0xeb,
+0x75,
+0x70,
+0x25,
+0x7d,
+0xa7,
+0xf2,
+0xdb,
+0x5e,
+0xa0,
+0x79,
+0x5d,
+0x3a,
+0xd5,
+0x60,
+0xbb,
+0x39,
+0x3c,
+0xe9,
+0x28,
+0x37,
+0xe7,
+0xd1,
+0xf0,
+0x74,
+0x1b,
+0x05,
+0xe7,
+0x7b,
+0x38,
+0xbe,
+0x30,
+0x15,
+0xe8,
+0x37,
+0x7a,
+0xc9,
+0xd1,
+0xc9,
+0x71,
+0xe3,
+0x56,
+0x0f,
+0xae,
+0x45,
+0xd9,
+0x26,
+0x43,
+0xcf,
+0x87,
+0x35,
+0x32,
+0xf9,
+0xb2,
+0x8c,
+0xed,
+0x80,
+0xbe,
+0xb7,
+0xa3,
+0x0e,
+0x43,
+0x6c,
+0xc1,
+0x9b,
+0x06,
+0x55,
+0x93,
+0xfe,
+0xdd,
+0x12,
+0x2b,
+0xcf,
+0x03,
+0xdd,
+0xa6,
+0x56,
+0xf2,
+0x7a,
+0x82,
+0xeb,
+0x81,
+0xf4,
+0x8a,
+0x43,
+0x5a,
+0xfe,
+0xd2,
+0x9d,
+0xb6,
+0x8e,
+0x62,
+0x6c,
+0x01,
+0x68,
+0x0a,
+0x65,
+0x9c,
+0xb5,
+0x50,
+0xdb,
+0xa8,
+0x6f,
+0xea,
+0x5d,
+0x79,
+0xce,
+0xee,
+0x66,
+0x7f,
+0xea,
+0x10,
+0x65,
+0x79,
+0x85,
+0xed,
+0x99,
+0x01,
+0xff,
+0xb0,
+0xa4,
+0xd1,
+0xc0,
+0xe5,
+0x6c,
+0x67,
+0x53,
+0x25,
+0x0f,
+0xbb,
+0xc6,
+0x27,
+0x93,
+0xfd,
+0x88,
+0x92,
+0xe6,
+0xed,
+0x4f,
+0xf4,
+0xfe,
+0xda,
+0xbf,
+0x3f,
+0x35,
+0x2e,
+0xad,
+0x6e,
+0xdc,
+0x0e,
+0xc5,
+0x60,
+0xc5,
+0x06,
+0xbf,
+0x9e,
+0x49,
+0x5f,
+0x4e,
+0xf6,
+0x19,
+0x0a,
+0x9a,
+0xa1,
+0x8b,
+0xe2,
+0xad,
+0x41,
+0x3d,
+0x6f,
+0x55,
+0x3d,
+0x68,
+0x71,
+0x66,
+0xbe,
+0x73,
+0xed,
+0x48,
+0xb1,
+0xfc,
+0xe8,
+0x7d,
+0x5a,
+0x6e,
+0x74,
+0x1e,
+0xa4,
+0x57,
+0xe6,
+0xee,
+0x90,
+0x44,
+0xfb,
+0x2d,
+0x68,
+0x96,
+0x39,
+0x4b,
+0x74,
+0x89,
+0x4c,
+0x84,
+0x48,
+0x42,
+0x55,
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+0x65,
+0x5c,
+0x10,
+0x2d,
+0xdc,
+0x54,
+0x0f,
+0xa5,
+0x7f,
+0x30,
+0x06,
+0x61,
+0x60,
+0xea,
+0xae,
+0xc3,
+0x17,
+0xb5,
+0x1f,
+0xcf,
+0xbe,
+0xa9,
+0x62,
+0x0a,
+0x8b,
+0x52,
+0x85,
+0xd2,
+0x12,
+0x73,
+0x64,
+0x7d,
+0xbe,
+0x84,
+0xc0,
+0xdc,
+0x9b,
+0xc6,
+0x5a,
+0x1a,
+0x3b,
+0xf4,
+0x1b,
+0xc0,
+0x9c,
+0x30,
+0xca,
+0x72,
+0x57,
+0xcc,
+0xca,
+0x6b,
+0x45,
+0x8e,
+0xd3,
+0xf1,
+0x61,
+0x55,
+0xc0,
+0xc2,
+0x13,
+0x08,
+0x0c,
+0x75,
+0x0b,
+0xbd,
+0x8d,
+0xe3,
+0xa0,
+0x76,
+0x73,
+0x66,
+0x9a,
+0x6f,
+0xa1,
+0x3c,
+0x19,
+0x12,
+0x75,
+0x1b,
+0xa9,
+0xc4,
+0x0f,
+0xbe,
+0xbc,
+0xbb,
+0x09,
+0x15,
+0x4b,
+0x3a,
+0x8b,
+0xc5,
+0x45,
+0x2e,
+0x91,
+0x1f,
+0x02,
+0xdb,
+0xa4,
+0x8b,
+0x4f,
+0xd9,
+0xd2,
+0xcd,
+0x57,
+0xdb,
+0x59,
+0x87,
+0x10,
+0xe7,
+0xde,
+0x22,
+0xec,
+0x2b,
+0x48,
+0xd3,
+0x21,
+0xc8,
+0x15,
+0xa3,
+0x25,
+0x31,
+0xf0,
+0x4f,
+0xf1,
+0x4b,
+0x73,
+0x73,
+0x09,
+0x67,
+0x80,
+0x3b,
+0x86,
+0xa2,
+0xc4,
+0x55,
+0xd5,
+0x89,
+0x87,
+0x9f,
+0x43,
+0x02,
+0x0e,
+0xe8,
+0xcc,
+0xa4,
+0xd4,
+0xc1,
+0x3c,
+0x84,
+0x52,
+0x6b,
+0x0f,
+0x53,
+0x89,
+0x04,
+0x7d,
+0xd0,
+0xed,
+0x83,
+0x2f,
+0x09,
+0xc4,
+0x3e,
+0xd6,
+0xb9,
+0xd0,
+0xa7,
+0x13,
+0x6b,
+0x85,
+0x99,
+0x22,
+0x6f,
+0xca,
+0x59,
+0xa0,
+0xdb,
+0x71,
+0x19,
+0x1f,
+0x37,
+0x00,
+0xe2,
+0x7b,
+0x46,
+0x81,
+0xd7,
+0x8e,
+0xdc,
+0x35,
+0x25,
+0x0f,
+0x8d,
+0x14,
+0xbd,
+0xfb,
+0x0e,
+0x14,
+0xbe,
+0x15,
+0x64,
+0xa4,
+0x55,
+0xad,
+0xc5,
+0xa3,
+0xd3,
+0xef,
+0x97,
+0x2a,
+0xa0,
+0x42,
+0xf7,
+0xb4,
+0x3e,
+0xc1,
+0x07,
+0xff,
+0x5c,
+0xe6,
+0x32,
+0x54,
+0x5b,
+0x71,
+0x32,
+0x24,
+0x82,
+0x21,
+0xf5,
+0xff,
+0x27,
+0x1b,
+0xbf,
+0x21,
+0x05,
+0x50,
+0x04,
+0x89,
+0x75,
+0xa4,
+0xdb,
+0x46,
+0x59,
+0xfc,
+0xc6,
+0xe5,
+0x06,
+0xe6,
+0x94,
+0x28,
+0x3e,
+0x22,
+0x6a,
+0x23,
+0x37,
+0x4c,
+0xc5,
+0xa1,
+0x88,
+0xe3,
+0xc1,
+0x8e,
+0x41,
+0xd0,
+0x01,
+0x1b,
+0x93,
+0x26,
+0xc8,
+0x26,
+0x78,
+0x78,
+0x77,
+0x51,
+0x59,
+0x7c,
+0x45,
+0x0e,
+0x8b,
+0xa7,
+0x99,
+0xc3,
+0x5e,
+0xb8,
+0xd5,
+0x25,
+0x78,
+0x4b,
+0xb0,
+0xdd,
+0x99,
+0xc7,
+0x9b,
+0xfc,
+0xb9,
+0x00,
+0x4e,
+0x3a,
+0x88,
+0xbd,
+0x94,
+0xf2,
+0x84,
+0x79,
+0x53,
+0x44,
+0x23,
+0x7c,
+0x17,
+0x4b,
+0xab,
+0xed,
+0xac,
+0x86,
+0x58,
+0x1b,
+0x94,
+0x16,
+0x8d,
+0xe8,
+0xb0,
+0x55,
+0x5e,
+0x11,
+0xc3,
+0x10,
+0x2d,
+0x53,
+0x7c,
+0x70,
+0xbc,
+0xd6,
+0x5b,
+0x23,
+0x3f,
+0x8b,
+0x57,
+0x23,
+0x8f,
+0xf5,
+0xdb,
+0x84,
+0x88,
+0x82,
+0x75,
+0xb0,
+0xa9,
+0xc6,
+0x90,
+0x0a,
+0xe7,
+0x68,
+0x5b,
+0x23,
+0xf0,
+0x08,
+0x46,
+0x43,
+0xe7,
+0x66,
+0x10,
+0xb5,
+0xe7,
+0x02,
+0xc8,
+0x8c,
+0x16,
+0x5e,
+0x0e,
+0x21,
+0xf8,
+0xc5,
+0xf9,
+0xee
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c
new file mode 100644
index 0000000000..363e673466
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c
@@ -0,0 +1,1645 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Microcode patch.
+ *
+ * Fam14 Microcode Patch rev 05000101 for 5020 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x14
+ * @e \$Revision: 37850 $   @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Encrypt Patch code 05000101 for 5020 and equivalent
+
+CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000101 =
+{{
+  0x11,
+  0x20,
+  0x06,
+  0x04,
+  0x01,
+  0x01,
+  0x00,
+  0x05,
+  0x01,
+  0x80,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x20,
+  0x50,
+  0x00,
+  0x00,
+  0x00,
+  0xaa,
+  0xaa,
+  0xaa,
+  0x01,
+  0xe9,
+  0xee,
+  0x42,
+  0x6b,
+  0x45,
+  0xbd,
+  0xcf,
+  0x76,
+  0xf0,
+  0x6d,
+  0x38,
+  0xf1,
+  0x7e,
+  0x5e,
+  0xb7,
+  0x22,
+  0x7d,
+  0xdb,
+  0x04,
+  0xff,
+  0xa4,
+  0xb6,
+  0x6c,
+  0x5d,
+  0x03,
+  0x3d,
+  0x35,
+  0x7d,
+  0x41,
+  0x02,
+  0x97,
+  0x28,
+  0xc9,
+  0x02,
+  0xd6,
+  0x84,
+  0xb6,
+  0x3d,
+  0xe6,
+  0x2f,
+  0x30,
+  0x3f,
+  0xc6,
+  0x8c,
+  0x5a,
+  0xe3,
+  0xbf,
+  0x50,
+  0x92,
+  0xd7,
+  0x1c,
+  0x86,
+  0xde,
+  0xb9,
+  0x48,
+  0x63,
+  0x02,
+  0xa2,
+  0xe6,
+  0x80,
+  0x7a,
+  0x73,
+  0x4f,
+  0xe8,
+  0xf7,
+  0xee,
+  0x3c,
+  0xfc,
+  0x8c,
+  0xf3,
+  0x9b,
+  0x34,
+  0x84,
+  0x37,
+  0x99,
+  0x4a,
+  0x8b,
+  0x7d,
+  0xbb,
+  0xa8,
+  0x30,
+  0xf0,
+  0x2f,
+  0xad,
+  0xac,
+  0x74,
+  0x14,
+  0x18,
+  0xa6,
+  0x49,
+  0x70,
+  0x2d,
+  0x75,
+  0xe1,
+  0x7e,
+  0x97,
+  0xa6,
+  0xd6,
+  0xc0,
+  0xc7,
+  0x7d,
+  0x4f,
+  0x1a,
+  0x69,
+  0xbf,
+  0xb6,
+  0xd5,
+  0x5e,
+  0xb8,
+  0x66,
+  0x63,
+  0xd7,
+  0xed,
+  0x5c,
+  0x07,
+  0x02,
+  0xb7,
+  0x9e,
+  0xc8,
+  0x41,
+  0x19,
+  0x1f,
+  0x72,
+  0x02,
+  0x5c,
+  0xa7,
+  0x58,
+  0xd2,
+  0x30,
+  0x42,
+  0x54,
+  0x4f,
+  0xd4,
+  0xc7,
+  0xc7,
+  0x5e,
+  0x35,
+  0x5e,
+  0x79,
+  0x9a,
+  0x82,
+  0x31,
+  0xa9,
+  0xe3,
+  0x56,
+  0x15,
+  0x63,
+  0x29,
+  0xe6,
+  0xfc,
+  0x8a,
+  0xa6,
+  0x50,
+  0x9b,
+  0xec,
+  0xe1,
+  0x1c,
+  0x1d,
+  0xef,
+  0xcb,
+  0x6f,
+  0x08,
+  0x4d,
+  0x8a,
+  0x5e,
+  0xa8,
+  0xb6,
+  0x97,
+  0x6c,
+  0x97,
+  0x32,
+  0x0b,
+  0x8a,
+  0x26,
+  0x44,
+  0xce,
+  0xdd,
+  0xbb,
+  0xdd,
+  0xa3,
+  0x53,
+  0xc1,
+  0x22,
+  0xfd,
+  0xf6,
+  0xb2,
+  0x5b,
+  0x94,
+  0x6e,
+  0x47,
+  0x48,
+  0xae,
+  0xc8,
+  0xfb,
+  0x5d,
+  0x43,
+  0x29,
+  0xd2,
+  0x37,
+  0xd6,
+  0xc0,
+  0x3c,
+  0x00,
+  0xb0,
+  0x8f,
+  0xa7,
+  0x4b,
+  0x9d,
+  0x33,
+  0xb3,
+  0x17,
+  0xfb,
+  0x12,
+  0x0e,
+  0x52,
+  0xe3,
+  0xd5,
+  0xfe,
+  0xf9,
+  0xf4,
+  0x25,
+  0xf3,
+  0x91,
+  0xe1,
+  0x9a,
+  0x26,
+  0x5a,
+  0x47,
+  0xfe,
+  0xb9,
+  0xb8,
+  0xc9,
+  0x12,
+  0x74,
+  0xca,
+  0x50,
+  0x54,
+  0x1e,
+  0x57,
+  0x39,
+  0x40,
+  0xec,
+  0x5e,
+  0x71,
+  0x07,
+  0xc4,
+  0x72,
+  0x58,
+  0xb1,
+  0xb8,
+  0xf9,
+  0x30,
+  0x39,
+  0x77,
+  0x8b,
+  0x7c,
+  0xaf,
+  0x08,
+  0xdf,
+  0x27,
+  0xae,
+  0x42,
+  0xe7,
+  0x45,
+  0xf0,
+  0x05,
+  0x9a,
+  0xfa,
+  0x30,
+  0x3f,
+  0xaf,
+  0x8b,
+  0xf0,
+  0xcf,
+  0xab,
+  0x48,
+  0x96,
+  0x65,
+  0x8e,
+  0xde,
+  0x3f,
+  0x9f,
+  0x65,
+  0x42,
+  0x96,
+  0x6a,
+  0x19,
+  0xb6,
+  0xb9,
+  0xd5,
+  0x53,
+  0x0c,
+  0x21,
+  0xe9,
+  0xd7,
+  0xf6,
+  0xd1,
+  0xc8,
+  0x59,
+  0x17,
+  0xdb,
+  0x77,
+  0x91,
+  0x19,
+  0xb9,
+  0xb9,
+  0xb6,
+  0x3a,
+  0x65,
+  0xbe,
+  0x65,
+  0x79,
+  0x77,
+  0x83,
+  0xc4,
+  0x9f,
+  0xae,
+  0xc5,
+  0x76,
+  0x29,
+  0x39,
+  0x44,
+  0x2f,
+  0x06,
+  0x6d,
+  0x08,
+  0xbb,
+  0x33,
+  0x27,
+  0x4e,
+  0x50,
+  0x43,
+  0x9f,
+  0x88,
+  0x28,
+  0xb6,
+  0x57,
+  0x8e,
+  0x53,
+  0x15,
+  0x20,
+  0xb0,
+  0xf8,
+  0x78,
+  0x24,
+  0x32,
+  0xf8,
+  0xf7,
+  0x45,
+  0x4b,
+  0x05,
+  0xa4,
+  0xe0,
+  0xbe,
+  0xfe,
+  0xc5,
+  0x70,
+  0xd3,
+  0xbe,
+  0x70,
+  0xd7,
+  0xa2,
+  0xf6,
+  0x33,
+  0x4f,
+  0x57,
+  0x34,
+  0xbc,
+  0x36,
+  0x3e,
+  0x78,
+  0x92,
+  0xfc,
+  0xcd,
+  0x4e,
+  0xe0,
+  0x64,
+  0x69,
+  0x4f,
+  0x49,
+  0x07,
+  0x07,
+  0x32,
+  0xba,
+  0x52,
+  0x01,
+  0xcb,
+  0xb7,
+  0x8f,
+  0x92,
+  0x4c,
+  0x0f,
+  0x6d,
+  0x27,
+  0x8c,
+  0x9c,
+  0x0a,
+  0x53,
+  0x5d,
+  0x70,
+  0xd8,
+  0xb2,
+  0x2f,
+  0xe5,
+  0x42,
+  0x10,
+  0x0f,
+  0x71,
+  0x90,
+  0x71,
+  0xea,
+  0x9c,
+  0x3d,
+  0xa4,
+  0x7f,
+  0x1a,
+  0xcc,
+  0x1b,
+  0xd3,
+  0x75,
+  0x6f,
+  0x3a,
+  0xaa,
+  0xa7,
+  0xaf,
+  0x97,
+  0x2c,
+  0xf4,
+  0x16,
+  0x03,
+  0xe0,
+  0x0c,
+  0xfc,
+  0xe8,
+  0x8b,
+  0x42,
+  0x5f,
+  0x4e,
+  0x6b,
+  0xc1,
+  0x99,
+  0x4a,
+  0x7f,
+  0x50,
+  0x45,
+  0x81,
+  0x51,
+  0x2c,
+  0xab,
+  0x1e,
+  0x90,
+  0x78,
+  0xf5,
+  0xb5,
+  0x41,
+  0xf0,
+  0x9d,
+  0xd1,
+  0x7e,
+  0x98,
+  0x16,
+  0x66,
+  0xba,
+  0xa3,
+  0xa3,
+  0xf5,
+  0x69,
+  0xa3,
+  0x5d,
+  0x64,
+  0x2d,
+  0x1f,
+  0x07,
+  0x5a,
+  0x84,
+  0x62,
+  0x6d,
+  0xa2,
+  0xa7,
+  0xbb,
+  0x12,
+  0x18,
+  0x33,
+  0x17,
+  0x57,
+  0x5f,
+  0x0a,
+  0x11,
+  0x6a,
+  0x39,
+  0x61,
+  0x9f,
+  0x77,
+  0x9e,
+  0xcc,
+  0xe6,
+  0x74,
+  0xee,
+  0x42,
+  0x16,
+  0x34,
+  0xf0,
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+  0x3e,
+  0x5d,
+  0x0c,
+  0xff,
+  0xee,
+  0xd7,
+  0x22,
+  0x6b,
+  0x6e,
+  0x8a,
+  0xf1,
+  0xa1,
+  0x1c,
+  0x59,
+  0x2c,
+  0x3f,
+  0x99,
+  0xcf,
+  0xea,
+  0x1b,
+  0x11,
+  0x23,
+  0x96,
+  0x80,
+  0x21,
+  0x58,
+  0xff,
+  0xc4,
+  0x6a,
+  0xb0,
+  0xd1,
+  0x7d,
+  0xd4,
+  0xe7,
+  0x1a,
+  0x68,
+  0xd7,
+  0x00
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c
new file mode 100644
index 0000000000..ec97a8dc47
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c
@@ -0,0 +1,187 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family 14 Ontario CPB Initialization
+ *
+ * Enables core performance boost.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x14/ON
+ * @e \$Revision: 46389 $   @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF14PowerMgmt.h"
+#include "GnbRegistersON.h"
+#include "NbSmuLib.h"
+#include "NbSmuLib.h"
+#include "cpuFeatures.h"
+#include "cpuCpb.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for checking whether or not CPB is supported.
+ *
+ * @param[in]  CpbServices             The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  Socket                  Zero based socket number to check.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     TRUE                    CPB is supported.
+ * @retval     FALSE                   CPB is not supported.
+ *
+ */
+BOOLEAN
+STATIC
+F14OnIsCpbSupported (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR             PciAddress;
+  CPB_CTRL_REGISTER    CpbControl;
+  CPU_LOGICAL_ID CpuFamilyRevision;
+
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
+    return FALSE;
+  } else {
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+    return (BOOLEAN) (CpbControl.NumBoostStates != 0);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for enabling Core Performance Boost.
+ *
+ * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
+ *
+ * @param[in]  CpbServices             The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  EntryPoint              Current CPU feature dispatch point.
+ * @param[in]  Socket                  Zero based socket number to check.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F14OnInitializeCpb (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT64                 EntryPoint,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR             PciAddress;
+  CPB_CTRL_REGISTER    CpbControl;
+  LPMV_SCALAR2_REGISTER  LpmvScalar2;
+  SMUx0B_x8580_STRUCT  SMUx0Bx8580;
+
+  if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
+    // F4x14C [25:24] ApmCstExtPol = 1
+    PciAddress.AddressValue = LPMV_SCALAR2_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
+    LpmvScalar2.ApmCstExtPol = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
+    // F4x15C [1:0] BoostSrc = 1
+    // F4x15C [29] BoostEnAllCores = 1
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+    CpbControl.BoostSrc = 1;
+    CpbControl.BoostEnAllCores = 1;
+    IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+  } else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
+    // Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
+    // interrupt the SMU with service index 12h.
+    NbSmuRcuRegisterRead (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, StdHeader);
+    SMUx0Bx8580.Field.PdmPeriod = 0x1388;
+    SMUx0Bx8580.Field.PdmParamLoc = 0;
+    SMUx0Bx8580.Field.PdmCacEn = 1;
+    SMUx0Bx8580.Field.PdmUnit = 1;
+    SMUx0Bx8580.Field.PdmEn = 1;
+    NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
+    NbSmuServiceRequest (0x12, TRUE, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport =
+{
+  0,
+  F14OnIsCpbSupported,
+  F14OnInitializeCpb
+};
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
index 3cadf73fc8..1e295889e2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
@@ -7,7 +7,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU/Family/0x14
- * @e \$Revision: 36418 $   @e \$Date: 2010-08-18 17:00:58 +0800 (Wed, 18 Aug 2010) $
+ * @e \$Revision: 48589 $   @e \$Date: 2011-03-10 09:27:00 -0700 (Thu, 10 Mar 2011) $
  *
  */
 /*
@@ -68,6 +68,14 @@
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+GetF14OnMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **OnEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
@@ -77,7 +85,8 @@ STATIC CONST UINT16 ROMDATA CpuF14MicrocodeEquivalenceTable[] =
 {
   0x5000, 0x5000,
   0x5001, 0x5001,
-  0x5010, 0x5010
+  0x5010, 0x5010,
+  0x5020, 0x5020
 };
 
 // Unencrypted equivalent
@@ -85,7 +94,8 @@ STATIC CONST UINT16 ROMDATA CpuF14UnEncryptedMicrocodeEquivalenceTable[] =
 {
   0x5000, 0x5800,
   0x5001, 0x5801,
-  0x5010, 0x5810
+  0x5010, 0x5810,
+  0x5020, 0x5820
 };
 
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
index f5f70bdfc7..620ed7d799 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
@@ -87,6 +87,14 @@ extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
  *----------------------------------------------------------------------------------------
  */
 VOID
+GetF14OnEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+
+VOID
 F14OnLoadMicrocodePatchAtEarly (
   IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
   IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
@@ -144,7 +152,7 @@ GetF14OnEarlyInitOnCoreTable (
 {
   *Table = F14OnEarlyInitOnCoreTable;
 
-  F14EarlySampleCoreSupport.F14GetEarlyInitTableHook (Table, StdHeader);
+  F14EarlySampleCoreSupport.F14GetEarlyInitTableHook ((const VOID **)Table, StdHeader);
 }
 
 /*---------------------------------------------------------------------------------------*/
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
index 82498c770b..ec502b0adb 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
@@ -66,6 +66,14 @@
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+GetF14OnLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **OnIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
@@ -84,6 +92,10 @@ STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF14OnLogicalIdAndRevArray[] =
   {
     0x5010,
     AMD_F14_ON_B0
+  },
+  {
+    0x5020,
+    AMD_F14_ON_C0
   }
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
index ba4b013d00..da445cc483 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
@@ -70,6 +70,14 @@ extern CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches;
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+GetF14OnMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **OnUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c
new file mode 100644
index 0000000000..37a03e84b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Ontario PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x14/ON
+ * @e \$Revision: 46389 $   @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14OnPciRegisters[] =
+{
+// Function 4
+
+// D18F4x104 - TDP Lock Accumulator
+// bits[1:0]   TdpLockDivVal = 1
+// bits[13:2]  TdpLockDivRate = 0x190
+// bits[16:15] TdpLockDivValCpu = 1
+// bits[28:17] TdpLockDivRateCpu = 0x190
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_14,                      // CpuFamily
+      AMD_F14_ON_Cx                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104),  // Address
+      0x03208641,                           // regData
+      0x1FFFBFFF,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F14OnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F14OnPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
index 226e951ec3..de100a2a06 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
@@ -112,6 +112,18 @@ CONST UINT16 ROMDATA F14MaxNbFreqAtMinVidFreqTable[] =
  *----------------------------------------------------------------------------------------
  */
 UINT32
+F14GetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+CORE_ID_POSITION
+F14CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
 STATIC
 RoundedDivision (
   IN       UINT32 Dividend,
@@ -300,6 +312,7 @@ F14NbPstateInit (
   UINT32                TargetNumerator;
   UINT32                TargetDenominator;
   BOOLEAN               ReturnStatus;
+  BOOLEAN               WaitForTransition;
   PCI_ADDR              PciAddress;
   D18F3xD4_STRUCT       Cptc0;
   D18F3xDC_STRUCT       Cptc2;
@@ -313,6 +326,7 @@ F14NbPstateInit (
   // F14 only supports NB P0 and NB P1
   ASSERT (TargetNbPstate < 2);
 
+  WaitForTransition = FALSE;
   ReturnStatus = TRUE;
 
   // Get D18F3xD4[MainPllOpFreqId] frequency
@@ -383,8 +397,11 @@ F14NbPstateInit (
     // Apply the appropriate P0 frequency
     PciAddress.AddressValue = CPTC2_PCI_ADDR;
     LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
+    if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) {
+      WaitForTransition = TRUE;
     Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv;
     LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
+    }
     NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv);
 
     // Determine NB P1 settings if necessary
@@ -434,6 +451,13 @@ F14NbPstateInit (
       NbP1Cof = 0;
     }
     *CurrentNbFreq = NbP0Cof;
+    if (WaitForTransition) {
+      // Ensure that the frequency has settled before returning to memory code.
+      PciAddress.AddressValue = CPTC2_PCI_ADDR;
+      do {
+        LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
+      } while (Cptc2.Field.NclkFreqDone != 1);
+    }
   } else {
     // Get NB P0 COF
     PciAddress.AddressValue = CPTC2_PCI_ADDR;
@@ -457,12 +481,7 @@ F14NbPstateInit (
         NbPsCfgLow.Field.NbPsForceSel = 1;
         LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
 
-        // Wait for the transition to complete.
-        PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
-        do {
-          LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
-        } while (NbPsCtrlSts.Field.NbPs1Act != 1);
-
+        WaitForTransition = TRUE;
         *CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv);
       } else {
         // No NB P-states.  Return FALSE, and set current frequency to P0.
@@ -476,15 +495,17 @@ F14NbPstateInit (
         // Request transition to P0
         NbPsCfgLow.Field.NbPsForceSel = 0;
         LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
+        WaitForTransition = TRUE;
       }
     }
-  }
-
+    if (WaitForTransition) {
   // Ensure that the frequency has settled before returning to memory code.
-  PciAddress.AddressValue = CPTC2_PCI_ADDR;
+      PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
   do {
-    LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
-  } while (Cptc2.Field.NclkFreqDone != 1);
+        LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
+      } while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate);
+    }
+  }
 
   return ReturnStatus;
 }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
index db19787391..e873bb14b4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
@@ -70,6 +70,22 @@
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+GetF14BrandIdString1 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString1Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetF14BrandIdString2 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString2Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
index 2d4e34d2d4..30ba2c1c18 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 40034 $   @e \$Date: 2010-10-19 04:03:22 +0800 (Tue, 19 Oct 2010) $
+ * @e \$Revision: 45203 $   @e \$Date: 2011-01-13 12:36:39 -0700 (Thu, 13 Jan 2011) $
  *
  */
 /*
@@ -77,6 +77,7 @@
 CONST CHAR8 ROMDATA str_AMD_C[] = "AMD C-";
 CONST CHAR8 ROMDATA str_AMD_E[] = "AMD E-";
 CONST CHAR8 ROMDATA str_AMD_G_T[] = "AMD G-T";
+CONST CHAR8 ROMDATA str_AMD_Z[] = "AMD Z-";
 
 // String2
 CONST CHAR8 ROMDATA str___Processor[] = " Processor";
@@ -88,6 +89,11 @@ CONST CHAR8 ROMDATA str_x_Processor[] = "x Processor";
 CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
 CONST CHAR8 ROMDATA str_N_Processor[] = "N Processor";
 CONST CHAR8 ROMDATA str_R_Processor[] = "R Processor";
+CONST CHAR8 ROMDATA str_E_Processor[] = "E Processor";
+CONST CHAR8 ROMDATA str_0D_APU[] = "0D APU with Radeon(tm) HD Graphics";
+CONST CHAR8 ROMDATA str_0_APU[] = "0 APU with Radeon(tm) HD Graphics";
+CONST CHAR8 ROMDATA str_5_APU[] = "5 APU with Radeon(tm) HD Graphics";
+CONST CHAR8 ROMDATA str_APU[] = " APU with Radeon(tm) HD Graphics";
 
 /*---------------------------------------------------------------------------------------
  *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
@@ -101,6 +107,7 @@ CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString1ArrayFt1[] =
   {2, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)},
   {1, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
   {2, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
+  {2, 0, 3, ON_SOCKET_FT1, str_AMD_Z, sizeof (str_AMD_Z)},
   {1, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)},
   {2, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)}
 };    //Cores, page, index, socket, stringstart, stringlength
@@ -126,6 +133,15 @@ CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString2ArrayFt1[] =
   {1, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
   {2, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
   {1, 0, 0x09, ON_SOCKET_FT1, str_R_Processor, sizeof (str_R_Processor)},
+  {2, 0, 0x09, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
+  {1, 0, 0x0A, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
+  {2, 0, 0x0A, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
+  {1, 0, 0x0B, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
+  {2, 0, 0x0B, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
+  {1, 0, 0x0C, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
+  {2, 0, 0x0C, ON_SOCKET_FT1, str_E_Processor, sizeof (str_E_Processor)},
+  {1, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
+  {2, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
   {1, 0, 0x0F, ON_SOCKET_FT1, 0, 0},    //Size 0 for no suffix
   {2, 0, 0x0F, ON_SOCKET_FT1, 0, 0},    //Size 0 for no suffix
  };    //Cores, page, index, socket, stringstart, stringlength
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
index dbead6d19f..8b8d30e0f6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
@@ -69,6 +69,14 @@
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+GetF14CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
index 50ce4d1cb8..aaf761f743 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
@@ -76,6 +76,33 @@ extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+DmiF14GetInfo (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINT8
+DmiF14GetVoltage (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINT16
+DmiF14GetMaxSpeed (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINT16
+DmiF14GetExtClock (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+DmiF14GetMemInfo (
+  IN OUT   CPU_GET_MEM_INFO  *CpuGetMemInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
@@ -147,16 +174,25 @@ DmiF14GetVoltage (
 {
   UINT8     MaxVid;
   UINT8     Voltage;
+  UINT8     NumberBoostStates;
   UINT64    MsrData;
+  PCI_ADDR  TempAddr;
+  CPU_LOGICAL_ID    CpuFamilyRevision;
+  CPB_CTRL_REGISTER CpbCtrl;
 
   // Voltage = 0x80 + (voltage at boot time * 10)
-  LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader);
-  MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid);
-  if (MaxVid == 0) {
-    LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
-    MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+    TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader);  // F4x15C
+    NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+  } else {
+    NumberBoostStates = 0;
   }
 
+  LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
+    MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+
   if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
     Voltage = 0;
   } else {
@@ -184,14 +220,27 @@ DmiF14GetMaxSpeed (
   IN       AMD_CONFIG_PARAMS  *StdHeader
   )
 {
+  UINT8  NumBoostStates;
   UINT32 P0Frequency;
+  UINT32 PciData;
+  PCI_ADDR PciAddress;
   PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+  CPU_LOGICAL_ID  CpuFamilyRevision;
 
   FamilyServices = NULL;
-  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
   ASSERT (FamilyServices != NULL);
 
-  FamilyServices->GetPstateFrequency (FamilyServices, (UINT8) 0x00, &P0Frequency, StdHeader);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C);
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    NumBoostStates = (UINT8) ((PciData >> 2) & 7);
+  } else {
+    NumBoostStates = 0;
+  }
+
+  FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader);
   return ((UINT16) P0Frequency);
 }
 
@@ -242,6 +291,10 @@ DmiF14GetMemInfo (
  * Processor Family Table
  *
  * Note: 'x' means we don't care this field
+ *       046h = "AMD C-Series Processor"
+ *       047h = "AMD E-Series Processor"
+ *       048h = "AMD S-Series Processor"
+ *       049h = "AMD G-Series Processor"
  *       002h = "Unknown"
  *-------------------------------------------------------------------------------------*/
 CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] =
@@ -250,6 +303,7 @@ CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] =
   // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
   {0, 0, 'x', 1, 0x46},
   {0, 0, 'x', 2, 0x47},
+  {0, 0, 'x', 4, 0x49},
   {'x', 'x', 'x', 'x', 0x02}
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
new file mode 100644
index 0000000000..98fe9f1896
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
@@ -0,0 +1,149 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Optimizations for lower power consumption
+ *
+ * Sets some registers for tablet parts at AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/F14
+ * @e \$Revision: 45578 $   @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF14PowerMgmt.h"
+#include "cpuF14LowPowerInit.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
+ * power consumption.
+ *
+ * Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate
+ * according to the BKDG.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F14OptimizeForLowPowerInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8                 NumBoostStates;
+  UINT32                LocalPciRegister;
+  BOOLEAN               OptimizeForLowPower;
+  BOOLEAN               IsRevC;
+  PCI_ADDR              PciAddress;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+
+  PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+  if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) &&
+      (CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
+    OptimizeForLowPower = TRUE;
+  } else {
+    OptimizeForLowPower = FALSE;
+  }
+
+  // Get F4x15C [4:2] NumBoostStates
+  // Get IsRevC
+  NumBoostStates = 0;
+  IsRevC = FALSE;
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
+    IsRevC = TRUE;
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+  }
+
+  // F6x94[2:0] CpuPstateThr
+  PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  if (OptimizeForLowPower) {
+    ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0;
+  } else {
+    if (NumBoostStates == 0) {
+      ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
+    } else {
+      ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
+    }
+  }
+  // F6x94[3] CpuPstateThrEn = 1
+  ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+  // F4x134[31:27] IntRateCC6DecrRate
+  PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  ((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h
new file mode 100644
index 0000000000..271036e16d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h
@@ -0,0 +1,77 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Optimizations for Low Power
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/F14
+ * @e \$Revision: 45578 $   @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _F14_LOW_POWER_INIT_H_
+#define _F14_LOW_POWER_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F14OptimizeForLowPowerInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _F14_LOW_POWER_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
index eeb417317d..6c5ce28410 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
@@ -7,7 +7,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 37263 $   @e \$Date: 2010-09-01 21:58:26 +0800 (Wed, 01 Sep 2010) $
+ * @e \$Revision: 48588 $   @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $
  *
  */
 /*
@@ -77,6 +77,21 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
 //  M S R    T a b l e s
 // ----------------------
 
+// MC0_CTL_MASK (0xC0010044)
+// bit[6] = 1, erratum #628
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_14,                       // CpuFamily
+      AMD_F14_ON_ALL                       // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_MC0_CTL_MASK,                      // MSR Address
+      0x0000000000000040,                    // OR Mask
+      0x0000000000000040,                    // NAND Mask
+     }}
+  },
 // MSR_TOM2 (0xC001001D)
 // bits[63:0] - TOP_MEM2 = 0
   {
@@ -85,12 +100,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
       AMD_FAMILY_14,                       // CpuFamily
       AMD_F14_ALL                          // CpuRevision
     },
-    AMD_PF_ALL,                            // platformFeatures
-    {
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
       MSR_TOM2,                              // MSR Address
       0x0000000000000000,                    // OR Mask
       0xFFFFFFFFFFFFFFFF,                    // NAND Mask
-    }
+    }}
   },
 // MSR_SYS_CFG (0xC0010010)
 // bit[21] - MtrrTom2En = 1
@@ -100,12 +115,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
       AMD_FAMILY_14,                       // CpuFamily
       AMD_F14_ALL                          // CpuRevision
     },
-    AMD_PF_ALL,                            // platformFeatures
-    {
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
       MSR_SYS_CFG,                           // MSR Address
       (1 << 21),                             // OR Mask
       (1 << 21),                             // NAND Mask
-    }
+    }}
   },
 // MSR_CPUID_EXT_FEATS (0xC0011005)
 // bit[41] - OSVW = 0
@@ -115,12 +130,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MSR_CPUID_EXT_FEATS,                   // MSR Address
       0x0000000000000000,                    // OR Mask
       0x0000020000000000,                    // NAND Mask
-    }
+    }}
   },
 // MSR_OSVW_ID_Length (0xC0010140)
 // bit[15:0] = 4
@@ -130,12 +145,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MSR_OSVW_ID_Length,                    // MSR Address
       0x0000000000000004,                    // OR Mask
       0x000000000000FFFF,                    // NAND Mask
-    }
+    }}
   },
 // MSR_HWCR (0xC0010015)
 // Do not set bit[24] = 1, it will be set in AmdInitPost.
@@ -149,12 +164,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
       AMD_FAMILY_14,                       // CpuFamily
       AMD_F14_ALL                          // CpuRevision
     },
-    AMD_PF_ALL,                            // platformFeatures
-    {
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
       MSR_MC0_CTL,                           // MSR Address
       0xFFFFFFFFFFFFFFFF,                    // OR Mask
       0xFFFFFFFFFFFFFFFF,                    // NAND Mask
-    }
+    }}
   },
 // MSR_LS_CFG (0xC0011020)
 // bit[36]  Reserved = 1, workaround for erratum #530
@@ -165,12 +180,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
       AMD_FAMILY_14,                       // CpuFamily
       AMD_F14_ALL                          // CpuRevision
     },
-    AMD_PF_ALL,                            // platformFeatures
-    {
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
       MSR_LS_CFG,                            // MSR Address
       0x0000001002000000,                    // OR Mask
       0x0000001002000000,                    // NAND Mask
-     }
+     }}
   },
 // MSR_DC_CFG (0xC0011022)
 // bit[57:56]  Reserved = 2
@@ -180,12 +195,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
       AMD_FAMILY_14,                       // CpuFamily
       AMD_F14_ALL                          // CpuRevision
     },
-    AMD_PF_ALL,                            // platformFeatures
-    {
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
       MSR_DC_CFG,                            // MSR Address
       0x0200000000000000,                    // OR Mask
       0x0300000000000000,                    // NAND Mask
-     }
+     }}
   }
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c
index aab474a865..1673a6dc8c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c
@@ -89,12 +89,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
       0x002E0800,                           // regData
       0x006E0800,                           // regMask
-    }
+    }}
   },
 
 // Function 2 - DRAM Controller
@@ -106,12 +106,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_2, 0xB8),  // Address
       0x00000000,                           // regData
       0xF000F000,                           // regMask
-    }
+    }}
   },
 // D18F2xBC
   {
@@ -120,12 +120,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_2, 0xBC),  // Address
       0x00000000,                           // regData
       0xC0000000,                           // regMask
-    }
+    }}
   },
 // D18F2x118 - Memory Controller Configuration Low
 // bits[7:6], MctPriHiWr = 10b
@@ -135,12 +135,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
       0x00000080,                           // regData
       0x000000C0,                           // regMask
-    }
+    }}
   },
 // D18F2x11C - Memory Controller Configuration High
 // bits[24:22], PrefConf = 1
@@ -150,12 +150,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x11C),  // Address
       0x00400000,                           // regData
       0x01C00000,                           // regMask
-    }
+    }}
   },
 
 // Function 3 - Misc. Control
@@ -168,12 +168,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40),  // Address
       0x00000100,                           // regData
       0x00000100,                           // regMask
-    }
+    }}
   },
 // D18F3x44 - MCA NB Configuration
 // bit[27]     NbMcaToMstCpuEn = 1
@@ -189,12 +189,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44),  // Address
       0x0A300040,                           // regData
       0x0A303E40,                           // regMask
-    }
+    }}
   },
 // D18F3x84 - ACPI Power State Control High
 // bit[18] Smaf6DramMemClkTri = 1
@@ -207,12 +207,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
       0x00060006,                           // regData
       0x00060006,                           // regMask
-    }
+    }}
   },
 // D18F3x8C - NB Configuration High
 // bit[26] EnConvertToNonIsoc = 1
@@ -222,12 +222,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
       0x04000000,                           // regData
       0x04000000,                           // regMask
-    }
+    }}
   },
 // D18F3xA0 - Power Control Miscellaneous
 // bit[9] SviHighFreqSel = 1
@@ -237,12 +237,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
       0x00000200,                           // regData
       0x00000200,                           // regMask
-    }
+    }}
   },
 // D18F3xA4 - Reported Temperature Control
 // bits[12:8] PerStepTimeDn = 0xF
@@ -256,12 +256,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4),  // Address
       0x00000FEF,                           // regData
       0x00001FFF,                           // regMask
-    }
+    }}
   },
 // D18F3xD4 - Clock Power Timing Control 0
 // bits[11:8]  ClkRampHystSel = 0xF
@@ -273,16 +273,16 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
       0x00024F00,                           // regData
       0x0002FF00,                           // regMask
-    }
+    }}
   },
 // D18F3xDC - Clock Power Timing Control 2
 // bits[29:27] NbClockGateHyst = 3
-// bit[30]     NbClockGateEn = 1
+// bit[30]     NbClockGateEn = 0 - erratum #596
 // bit[31]     CnbCifClockGateEn = 1
   {
     PciRegister,
@@ -290,12 +290,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
-      0xD8000000,                           // regData
+      0x98000000,                           // regData
       0xF8000000,                           // regMask
-    }
+    }}
   },
 // D18F3x180 - Extended NB MCA Configuration
 // bit[2]   WDTCntSel[3] = 0
@@ -307,12 +307,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
       0x00200020,                           // regData
       0x00200024,                           // regMask
-    }
+    }}
   },
 // D18F3x188 - NB Extended Configuration
 // bit[21]      EnCpuSerWrBehindIoRd = 0
@@ -325,12 +325,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
       0x1B000000,                           // regData
       0xFFA00000,                           // regMask
-    }
+    }}
   },
 
 // Function 4 - Extended Misc. Control
@@ -344,12 +344,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
       0x00000000,                           // regData
       0x00000707,                           // regMask
-    }
+    }}
   },
 // D18F4x124 - C-state Monitor Control 1
 // bit[15]      TimerTickIntvlScale = 1
@@ -364,12 +364,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
       0x05138000,                           // regData
       0x07FF8000,                           // regMask
-    }
+    }}
   },
 // D18F4x134 - C-state Monitor Control 3
 // bits[3:0]    IntRatePkgC6MaxDepth = 0
@@ -379,19 +379,18 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
 // bits[19:16]  IntRateCC6MaxDepth = 5
 // bits[23:20]  IntRateCC6Threshold = 4
 // bits[26:24]  IntRateCC6BurstLen = 5
-// bits[31:27]  IntRateCC6DecrRate = 0x08
   {
     PciRegister,
     {
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address
-      0x45455100,                           // regData
-      0xFFFFFFFF,                           // regMask
-    }
+      0x05455100,                           // regData
+      0x07FFFFFF,                           // regMask
+    }}
   },
 // D18F4x13C - SMAF Code DID 1
 // bits[4:0]    Smaf4Did = 0x0F
@@ -402,12 +401,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address
       0x000F000F,                           // regData
       0x001F001F,                           // regMask
-    }
+    }}
   },
 // D18F4x1A4 - C-state Monitor Mask
 // bits[7:0]    IntRateMonMask = 0xFC
@@ -420,12 +419,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address
       0xFFFFFFFC,                           // regData
       0xFFFFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F4x1A8 - CPU State Power Management Dynamic Control 0
 // bits[4:0]   SingleHaltCpuDid = 0x1E
@@ -439,12 +438,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address
       0x009003FE,                           // regData
       0x00F083FF,                           // regMask
-    }
+    }}
   },
 // D18F4x1AC - CPU State Power Management Dynamic Control 1
 // bits[9:5]  C6Did = 0x1F
@@ -456,12 +455,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address
       0x300003E0,                           // regData
       0x300003E0,                           // regMask
-    }
+    }}
   },
 // D18F6x50 - Configuration Register Access Control
 // bit[1]  CfgAccAddrMode = 0
@@ -471,12 +470,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50),  // Address
       0x00000000,                           // regData
       0x00000002,                           // regMask
-    }
+    }}
   },
 // D18F6x54 - DRAM Arbitration Control FEQ Collision
 // bits[7:0]    FeqLoPrio = 0x20
@@ -489,12 +488,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54),  // Address
       0x00081020,                           // regData
       0x80FFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x58 - DRAM Arbitration Control Display Collision
 // bits[7:0]    DispLoPrio = 0x40
@@ -507,12 +506,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58),  // Address
       0x00102040,                           // regData
       0xFFFFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x5C - DRAM Arbitration Control FEQ Write Protect
 // bits[7:0]    FeqLoPrio = 0x20
@@ -525,12 +524,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C),  // Address
       0x00081020,                           // regData
       0x80FFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x60 - DRAM Arbitration Control Display Write Protect
 // bits[7:0]    DispLoPri = 0x20
@@ -543,12 +542,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60),  // Address
       0x00081020,                           // regData
       0xFFFFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x64 - DRAM Arbitration Control FEQ Read Protect
 // bits[7:0]    FeqLoPrio = 0x10
@@ -561,12 +560,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64),  // Address
       0x00040810,                           // regData
       0x80FFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x68 - DRAM Arbitration Control Display  Read Protect
 // bits[7:0]    DispLoPrio = 0x10
@@ -579,12 +578,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68),  // Address
       0x00040810,                           // regData
       0xFFFFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x6C - DRAM Arbitration Control FEQ Fairness Timer
 // bits[7:0]    FeqLoPrio = 0x80
@@ -596,12 +595,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C),  // Address
       0x00204080,                           // regData
       0x00FFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x70 - DRAM Arbitration Control Display Fairness Timer
 // bits[7:0]    DispLoPrio = 0x80
@@ -614,12 +613,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70),  // Address
       0x00204080,                           // regData
       0xFFFFFFFF,                           // regMask
-    }
+    }}
   },
 // D18F6x74 - Dram Idle Page Close Limit
 // bits[40]    IdleLimit = 0x1E
@@ -629,12 +628,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x74),  // Address
       0x0000001E,                           // regData
       0x0000001F,                           // regMask
-    }
+    }}
   },
 // D18F6x78 - Dram Prioritization and Arbitration Control
 // bits[1:0]    DispDbePrioEn = 3
@@ -648,12 +647,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78),  // Address
       0x00000037,                           // regData
       0x0000007F,                           // regMask
-    }
+    }}
   },
 // D18F6x90 - NB P-state Config Low
 // As part of BIOS Requirements for NB P-state Initialization
@@ -666,16 +665,14 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90),  // Address
       0x50000000,                           // regData
       0x70000000,                           // regMask
-    }
+    }}
   },
 // D18F6x94 - NB P-state Config High
-// bits[2:0]    CpuPstateThr = 1
-// bit[3]       CpuPstateThrEn = 1
 // bits[25:23]  NbPsC0Timer = 4
   {
     PciRegister,
@@ -683,12 +680,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94),  // Address
-      0x02000009,                           // regData
-      0x0380000F,                           // regMask
-    }
+      0x02000000,                           // regData
+      0x03800000,                           // regMask
+    }}
   },
 // D18F6x9C - NCLK Reduction Control
 // bits[6:0]   NclkRedDiv = 0x60
@@ -700,12 +697,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C),  // Address
       0x000001E0,                           // regData
       0x000001FF,                           // regMask
-    }
+    }}
   }
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
index b75e69fac5..8ca7bc524f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
@@ -86,12 +86,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PerCorePciRegisters[] =
       AMD_FAMILY_14,                      // CpuFamily
       AMD_F14_ALL                         // CpuRevision
     },
-    AMD_PF_ALL,                           // platformFeatures
-    {
+	{AMD_PF_ALL},                           // platformFeatures
+    {{
       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC),  // Address
       0x00000100,                           // regData
       0x0000010F,                           // regMask
-    }
+    }}
   }
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
index 53e6df5163..6a1d15ab5c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
@@ -10,7 +10,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU/F14
- * @e \$Revision: 39744 $   @e \$Date: 2010-10-15 02:18:02 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 46951 $   @e \$Date: 2011-02-11 12:37:59 -0700 (Fri, 11 Feb 2011) $
  *
  */
 /*
@@ -51,7 +51,6 @@
  */
 #include "AGESA.h"
 #include "amdlib.h"
-#include "cpuCacheInit.h"
 #include "cpuF14PowerMgmt.h"
 #include "cpuRegisters.h"
 #include "cpuApicUtilities.h"
@@ -60,7 +59,6 @@
 #include "cpuEarlyInit.h"
 #include "cpuFamilyTranslation.h"
 #include "cpuF14PowerCheck.h"
-#include "cpuF14Utilities.h"
 #include "Filecode.h"
 #define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE
 
@@ -100,18 +98,18 @@ F14PmPwrChkCopyPstate (
 
 /*---------------------------------------------------------------------------------------*/
 /**
- * Family 14h core 0 entry point for performing the family 14h Processor-
+ * Family 14h Ontario core 0 entry point for performing the family 14h Ontario Processor-
  * Systemboard Power Delivery Check.
  *
  * The steps are as follows:
- *    1. Starting with P0, loop through all P-states until a passing state is
+ *    1. Starting with hardware P0, loop through all P-states until a passing state is
  *       found.  A passing state is one in which the current required by the
  *       CPU is less than the maximum amount of current that the system can
  *       provide to the CPU.  If P0 is under the limit, no further action is
  *       necessary.
  *    2. If at least one P-State is under the limit & at least one P-State is
  *       over the limit, the BIOS must:
- *       a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
+ *       a. Program D18F4x15C[BoostSrc]=0.
  *       b. If the processor's current P-State is disabled by the power check,
  *          then the BIOS must request a transition to an enabled P-state
  *          using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
@@ -126,7 +124,7 @@ F14PmPwrChkCopyPstate (
  *          1. D18F3x64[HtcPstateLimit]
  *          2. D18F3xDC[PstateMaxVal]
  *    3. If all P-States are over the limit, the BIOS must:
- *       a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
+ *       a. Program D18F4x15C[BoostSrc]=0.
  *       b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then
  *          write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
  *          MSRC001_0063[CurPstate] to reflect the new value.
@@ -151,17 +149,24 @@ F14PmPwrCheck (
   IN       AMD_CONFIG_PARAMS     *StdHeader
   )
 {
-  UINT8       DisPsNum;
+  UINT8       DisHwPsNum;
+  UINT8       DisSwPsNum;
   UINT8       PsMaxVal;
   UINT8       Pstate;
+  UINT8       PstateLimit;
+  UINT8       NumberBoostStates;
   UINT32      ProcIddMax;
-  UINT32      PciRegister;
   UINT32      Socket;
   UINT32      Module;
   UINT32      Core;
-  UINT32      PstateLimit;
   PCI_ADDR    PciAddress;
-  UINT64      MsrRegister;
+  UINT64      LocalMsrRegister;
+  BOOLEAN     ThermalPstateEn;
+  NB_CAPS_REGISTER              NbCaps;
+  HTC_REGISTER                  HtcReg;
+  CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
+  CPB_CTRL_REGISTER             CpbCtrl;
+  CPU_LOGICAL_ID                CpuFamilyRevision;
   AP_TASK     TaskPtr;
   AGESA_STATUS IgnoredSts;
   PWRCHK_ERROR_DATA ErrorData;
@@ -172,17 +177,53 @@ F14PmPwrCheck (
 
   ASSERT (Core == 0);
 
+  // save ThermalPstateEn
+  //   TRUE if the P-state indicated by D18F3x64[HtcPstateLimit] is enabled;
+  //   FALSE otherwise.
+  PciAddress.AddressValue = HTC_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
+  LibAmdMsrRead (PS_REG_BASE + HtcReg.HtcPstateLimit, &LocalMsrRegister, StdHeader);
+  if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+    ThermalPstateEn = TRUE;
+  } else {
+    ThermalPstateEn = FALSE;
+  }
+
   // get the Max P-state value
   for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
-    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
       break;
     }
   }
 
   ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
 
-  DisPsNum = 0;
+  // get NumberBoostStates
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
+    NumberBoostStates = 0;
+  } else {
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader);  // D18F4x15C
+    NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+  }
+
+  // update PstateMaxVal if warranted by HtcPstateLimit
+  PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
+  if (NbCaps.HtcCapable == 1) {
+    if (HtcReg.HtcTmpLmt != 0) {
+      PciAddress.AddressValue = CPTC2_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+      if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) {
+        ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+      }
+    }
+  }
+
+  DisHwPsNum = 0;
   for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
     if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
       if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
@@ -190,17 +231,23 @@ F14PmPwrCheck (
         PutEventLog (AGESA_WARNING,
                      CPU_EVENT_PM_PSTATE_OVERCURRENT,
                      Socket, Pstate, 0, 0, StdHeader);
-        DisPsNum++;
+        DisHwPsNum++;
       } else {
         break;
       }
     }
   }
 
+  // get the number of software Pstate that is disabled by delivery check
+  if (NumberBoostStates < DisHwPsNum) {
+    DisSwPsNum = DisHwPsNum - NumberBoostStates;
+  } else {
+    DisSwPsNum = 0;
+  }
   // If all P-state registers are disabled, move P[PsMaxVal] to P0
   // and transition to P0, then wait for CurPstate = 0
 
-  ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
+  ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisHwPsNum);
 
   // We only need to log this event on the BSC
   if (ErrorData.AllowablePstateNumber == 0) {
@@ -209,7 +256,15 @@ F14PmPwrCheck (
                  Socket, 0, 0, 0, StdHeader);
   }
 
-  if (DisPsNum != 0) {
+  if (DisHwPsNum != 0) {
+    // Program F4x15C[BoostSrc] = 0
+    if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+      PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader);  // D18F4x15C
+      CpbCtrl.BoostSrc = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &CpbCtrl, StdHeader);  // D18F4x15C
+    }
+
     TaskPtr.FuncAddress.PfApTaskI = F14PmPwrCheckCore;
     TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
     TaskPtr.DataTransfer.DataPtr = &ErrorData;
@@ -220,28 +275,32 @@ F14PmPwrCheck (
     // Final Step
     //    D18F3x64[HtPstatelimit] -= disPsNum
     //    D18F3xDC[PstateMaxVal]-= disPsNum
-
     PciAddress.AddressValue = HTC_PCI_ADDR;
-    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
-    PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit;
-    if (PstateLimit > DisPsNum) {
-      PstateLimit -= DisPsNum;
+    LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
+    PciAddress.AddressValue = NB_CAPS_PCI_ADDR; // D18F3xE8
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
+    if (ThermalPstateEn || HtcReg.HtcTmpLmt == 0 || NbCaps.HtcCapable == 0) {
+      PstateLimit = (UINT8) HtcReg.HtcPstateLimit;
+      if (PstateLimit > DisHwPsNum) {
+        PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
     } else {
-      PstateLimit = 0;
+        PstateLimit = NumberBoostStates;
     }
-    ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit = PstateLimit;
-    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
+      HtcReg.HtcPstateLimit = PstateLimit;
+      PciAddress.AddressValue = HTC_PCI_ADDR;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
 
     PciAddress.AddressValue = CPTC2_PCI_ADDR;
-    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
-    PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
-    if (PstateLimit > DisPsNum) {
-      PstateLimit -= DisPsNum;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+      PstateLimit = (UINT8) ClkPwrTimingCtrl2.PstateMaxVal;
+      if (PstateLimit > DisHwPsNum) {
+        PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
     } else {
-      PstateLimit = 0;
+        PstateLimit = NumberBoostStates;
+      }
+      ClkPwrTimingCtrl2.PstateMaxVal = PstateLimit;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
     }
-    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PstateLimit;
-    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
   }
 }
 
@@ -265,37 +324,64 @@ F14PmPwrCheckCore (
   )
 {
   UINT8  i;
-  UINT8  PsMaxVal;
-  UINT8  DisPsNum;
-  UINT8  CurrentPs;
-  UINT64 MsrRegister;
+  UINT8  HardwarePsMaxVal;
+  UINT8  DisHwPsNum;
+  UINT8  DisSwPsNum;
+  UINT8  CurrentSoftwarePs;
+  UINT8  CurrentHardwarePs;
+  UINT8  NumberBoostStates;
+  UINT64 LocalMsrRegister;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              PciAddress;
+  CPB_CTRL_REGISTER     CpbCtrl;
   CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
 
-  PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
-  DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
+  HardwarePsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
+  DisHwPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
              ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
 
-  LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
-  CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
+  LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+  CurrentSoftwarePs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
+
+  if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
+    NumberBoostStates = 0;
+  } else {
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader);  // D18F4x15C
+    NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+  }
+
+  CurrentHardwarePs = CurrentSoftwarePs + NumberBoostStates;
+
+  if (NumberBoostStates < DisHwPsNum) {
+    DisSwPsNum = DisHwPsNum - NumberBoostStates;
+  } else {
+    DisSwPsNum = 0;
+  }
 
   if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
 
     // Step 1
     // Transition to Pstate Max if not there already
 
-    if (CurrentPs != PsMaxVal) {
-      FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
+    if (CurrentHardwarePs != HardwarePsMaxVal) {
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
+      CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
     }
 
 
     // Step 2
-    // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
+    // If CurrentSoftwarePs is not P0, copy CurrentSoftwarePs contents to Software P0 and switch
     // to P0.
 
-    if (PsMaxVal != 0) {
-      F14PmPwrChkCopyPstate (0, PsMaxVal, StdHeader);
+    if (CurrentSoftwarePs != 0) {
+      F14PmPwrChkCopyPstate (NumberBoostStates, CurrentSoftwarePs, StdHeader);
+      LibAmdMsrRead ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
+      ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 1;
+      LibAmdMsrWrite ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
       FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
     }
   } else {
@@ -304,29 +390,39 @@ F14PmPwrCheckCore (
     // Step 1
     // Transition to a valid Pstate if current Pstate has been disabled
 
-    if (CurrentPs < DisPsNum) {
-      FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
-      CurrentPs = DisPsNum;
+    if (CurrentHardwarePs < DisHwPsNum) {
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
+      CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
     }
 
+    if (DisSwPsNum != 0) {
     // Step 2
     // Move enabled Pstates up and disable the remainder
 
-    for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
-      F14PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader);
+      for (i = 0; (i + DisHwPsNum) <= HardwarePsMaxVal; ++i) {
+        F14PmPwrChkCopyPstate ((i + NumberBoostStates), (i + DisHwPsNum), StdHeader);
     }
-
     // Step 3
     // Transition to current COF/VID at shifted location
 
-    CurrentPs = (CurrentPs - DisPsNum);
-    FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
+      CurrentSoftwarePs = (CurrentSoftwarePs - DisSwPsNum);
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSoftwarePs, (BOOLEAN) TRUE, StdHeader);
+    }
+  }
+
+  if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
+    // only software P0 should be enabled.
+    i = NumberBoostStates + 1;
+  } else {
+    if (DisSwPsNum == 0) {
+      // No software Pstate is disabed, set i = HardwarePsMaxVal + 1 to skip below 'while loop'.
+      i = HardwarePsMaxVal + 1;
+    } else {
+      // get the first software Pstate that should be disabled.
+      i = HardwarePsMaxVal - DisSwPsNum + 1;
   }
-  i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
-  if (i == 0) {
-    i++;
   }
-  while (i <= PsMaxVal) {
+  while (i <= HardwarePsMaxVal) {
     FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
     i++;
   }
@@ -350,9 +446,9 @@ F14PmPwrChkCopyPstate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 LocalMsrRegister;
 
-  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
-  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
+  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
 }
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h
index 72cf02f5c4..f0d8198ec1 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h
@@ -7,7 +7,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU/F14
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 46836 $   @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
  *
  */
 /*
@@ -110,6 +110,20 @@ typedef struct {
 } PSTATE_MSR;
 
 
+/* COFVID Control Register 0xC0010070 */
+#define MSR_COFVID_CTL 0xC0010070
+
+/// COFVID Control MSR Register
+typedef struct {
+  UINT64 CpuDid:4;                   ///< CPU core divisor identifier
+  UINT64 CpuDidMSD:5;                ///< CPU core frequency identifier
+  UINT64 CpuVid:7;                   ///< CPU core VID
+  UINT64 PstateId:3;                 ///< P-state identifier
+  UINT64 IgnoreFidVidDid:1;          ///< Ignore FID, VID, and DID
+  UINT64 :44;                        ///< Reserved
+} COFVID_CTRL_MSR;
+
+
 /* COFVID Status Register 0xC0010071 */
 #define MSR_COFVID_STS 0xC0010071
 
@@ -301,6 +315,36 @@ typedef struct {
   UINT32 :16;                        ///< Reserved
 } CLK_PWR_TIMING_CTRL3_REGISTER;
 
+/* Local hardware thermal control register D18F3x138 */
+#define LHTC_REG 0x138
+#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG))
+
+/// Local Hardware Thermal Control PCI Register
+typedef struct {
+  UINT32 LHtcEn:1;                   ///< Local HTC Enable
+  UINT32 :7;                         ///< Reserved
+  UINT32 LHtcAct:2;                  ///< Local HTC Active State
+  UINT32 :2;                         ///< Reserved
+  UINT32 LHtcActSts:2;               ///< Local HTC Active Status
+  UINT32 :2;                         ///< Reserved
+  UINT32 LHtcTmpLmt:7;               ///< Local HTC temperature limit
+  UINT32 LHtcSlewSel:1;              ///< Local HTC slew-controlled temp select
+  UINT32 LHtcHystLmt:4;              ///< Local HTC hysteresis
+  UINT32 LHtcPstateLimit:3;          ///< Local HTC P-state limit select
+  UINT32 LHtcLock:1;                 ///< HTC lock
+} LHTC_REGISTER;
+
+/* Product Information Register D18F3x1FC */
+#define PRODUCT_INFO_REG 0x1FC
+#define PRODUCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRODUCT_INFO_REG))
+
+/// Product Information PCI Register
+typedef struct {
+  UINT32 :2;                         ///< Reserved
+  UINT32 LowPowerDefault:1;          ///< Low Power Default
+  UINT32 :29;                        ///< Reserved
+} PRODUCT_INFO_REGISTER;
+
 
 /* C-state Control 1 Register D18F4x118 */
 #define CSTATE_CTRL1_REG 0x118
@@ -336,6 +380,33 @@ typedef struct {
 } CSTATE_CTRL2_REGISTER;
 
 
+/* C-state Monitor Control 3 Register D18F4x134 */
+#define CSTATE_MON_CTRL3_REG 0x134
+#define CSTATE_MON_CTRL3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_MON_CTRL3_REG))
+
+/// C-state Monitor Control 3 Register
+typedef struct {
+  UINT32 IntRatePkgC6MaxDepth:4;     ///< Interrupt rate monitor PC6 maximum counter depth
+  UINT32 IntRatePkgC6Threshold:4;    ///< Interrupt rate monitor PC6 threshold
+  UINT32 IntRatePkgC6BurstLen:3;     ///< Interrupt rate monitor PC6 burst length
+  UINT32 IntRatePkgC6DecrRate:5;     ///< Interrupt rate monitor PC6 decrement rate
+  UINT32 IntRateCC6MaxDepth:4;       ///< Interrupt rate monitor CC6 maximum counter depth
+  UINT32 IntRateCC6Threshold:4;      ///< Interrupt rate monitor CC6 threshold
+  UINT32 IntRateCC6BurstLen:3;       ///< Interrupt rate monitor CC6 burst length
+  UINT32 IntRateCC6DecrRate:5;       ///< Interrupt rate monitor CC6 decrement rate
+} CSTATE_MON_CTRL3_REGISTER;
+
+/* LPMV Scalar 2 Register D18F4x14C */
+#define LPMV_SCALAR2_REG 0x14C
+#define LPMV_SCALAR2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, LPMV_SCALAR2_REG))
+
+/// LPMV Scalar 2 Register
+typedef struct {
+  UINT32 :24;                        ///< Reserved
+  UINT32 ApmCstExtPol:2;             ///< Number of boosted states
+  UINT32 :6;                         ///< Reserved
+} LPMV_SCALAR2_REGISTER;
+
 /* Core Performance Boost Control Register D18F4x15C */
 #define CPB_CTRL_REG 0x15C
 #define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
index 44e31d7e8c..b234541959 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
@@ -7,7 +7,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 37018 $   @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
+ * @e \$Revision: 45626 $   @e \$Date: 2011-01-19 09:58:02 -0700 (Wed, 19 Jan 2011) $
  *
  */
 /*
@@ -55,6 +55,7 @@
 #include "cpuF14SoftwareThermal.h"
 #include "cpuF14PowerPlane.h"
 #include "cpuF14PowerCheck.h"
+#include "cpuF14LowPowerInit.h"
 #include "Filecode.h"
 #define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE
 
@@ -73,6 +74,14 @@
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+GetF14SysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
@@ -91,6 +100,13 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
     F14PmPwrPlaneInit                           // Function Pointer
   },
 
+  // Step x - Optimizations for lower power
+  //   Execute both cold & warm
+  {
+    0,                                                // ExeFlags
+    F14OptimizeForLowPowerInit                // Function Pointer
+  },
+
   // Step 2 - Current Delivery Check
   //   Execute both cold & warm
   {
@@ -103,7 +119,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
   {
     0,                                                // ExeFlags
     F14PmThermalInit                            // Function Pointer
-  },
+  }
 };
 
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
index 6464954051..048116020f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
@@ -57,6 +57,7 @@
 #include "cpuFamilyTranslation.h"
 #include "cpuServices.h"
 #include "cpuF14PowerMgmt.h"
+#include "cpuF14PowerPlane.h"
 #include "OptionFamily14hEarlySample.h"
 #include "NbSmuLib.h"
 #include "GnbRegistersON.h"
@@ -129,7 +130,7 @@ F14PmPwrPlaneInit (
   )
 {
   UINT32                SystemSlewRate;
-  UINT32                PciRegister;
+  UINT32                PciReg;
   UINT32                WaitTime;
   UINT32                VSRampSlamTime;
   PCI_ADDR              PciAddress;
@@ -166,9 +167,9 @@ F14PmPwrPlaneInit (
 
   // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
   PciAddress.AddressValue = CPTC1_PCI_ADDR;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-  ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampSlamTime = VSRampSlamTime;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+  ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciReg)->VSRampSlamTime = VSRampSlamTime;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
 
   // Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
   F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
@@ -180,11 +181,11 @@ F14PmPwrPlaneInit (
   F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
 
   PciAddress.AddressValue = CPTC2_PCI_ADDR;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
+  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
 }
 
 /*---------------------------------------------------------------------------------------*/
@@ -211,7 +212,7 @@ F14PmVrmLowPowerModeEnable (
   UINT32    PstateCurrent;
   UINT32    NextPstateCurrent;
   UINT32    NextPstateCurrentRaw;
-  UINT32    PciRegister;
+  UINT32    PciReg;
   UINT32    PreviousVid;
   UINT32    CurrentVid;
   UINT64    PstateMsr;
@@ -249,24 +250,24 @@ F14PmVrmLowPowerModeEnable (
     }
   }
   PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
   if (IsPsiEnabled) {
-    ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVid = CurrentVid;
-    ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 1;
+    ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVid = CurrentVid;
+    ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 1;
   } else {
-    ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 0;
+    ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 0;
   }
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
 
 
   // Set up NBPSI_L for VDDNB
   PciAddress.AddressValue = CPTC3_PCI_ADDR;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
   if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) {
-    ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVid = 0;
-    ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 1;
+    ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVid = 0;
+    ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 1;
   } else {
-    ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 0;
+    ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 0;
   }
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
 }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
index d37f3fd32a..64bcf95697 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU/F14
- * @e \$Revision: 37010 $   @e \$Date: 2010-08-28 03:10:12 +0800 (Sat, 28 Aug 2010) $
+ * @e \$Revision: 44325 $   @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
  *
  */
 /*
@@ -75,6 +75,49 @@
  *----------------------------------------------------------------------------------------
  */
 
+AGESA_STATUS
+F14GetPstateTransLatency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F14GetPstateFrequency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F14GetPstatePower (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F14GetPstateMaxState (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+     OUT   UINT32              *MaxPStateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+F14GetPstateRegisterInfo (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+     OUT   UINT32              *SwPstateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
@@ -154,8 +197,8 @@ F14GetPstateFrequency (
   UINT32 CpuDidLSD;
   UINT32 CpuDidMSD;
   UINT32 CoreClkDivisor;
-  UINT32 PciRegister;
-  UINT64 MsrRegister;
+  UINT32 PciReg;
+  UINT64 MsrReg;
   BOOLEAN FrequencyCalculated;
   BOOLEAN ClockDivisorCalculated;
   PCI_ADDR PciAddress;
@@ -164,11 +207,11 @@ F14GetPstateFrequency (
 
   ASSERT (StateNumber < NM_PS_REG);
 
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
 
-  CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidLSD);
-  CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidMSD);
+  CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidLSD);
+  CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidMSD);
 
   FrequencyCalculated = FALSE;
   ClockDivisorCalculated = FALSE;
@@ -194,10 +237,10 @@ F14GetPstateFrequency (
   if (!FrequencyCalculated) {
     // Get D18F3xD4[MainPllOpFreqId] frequency
     PciAddress.AddressValue = CPTC0_PCI_ADDR;
-    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
 
-    if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
-      MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
+    if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
+      MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
     } else {
       MainPllFid = 0;
     }
@@ -234,14 +277,14 @@ F14GetPstatePower (
   UINT32  IddDiv;
   UINT32  V_x10000;
   UINT32  Power;
-  UINT64  MsrRegister;
+  UINT64  MsrReg;
 
   ASSERT (StateNumber < NM_PS_REG);
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
-  CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
-  IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
-  IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+  CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
+  IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue);
+  IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv);
 
   if (CpuVid >= 0x7C) {
     V_x10000 = 0;
@@ -289,13 +332,19 @@ F14GetPstateMaxState (
   )
 {
   UINT64              MsrValue;
+  UINT32              PciReg;
+  PCI_ADDR            PciAddress;
+
+  // For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // D18F4x15C
 
   //
   // Read PstateMaxVal [6:4] from MSR C001_0061
   // So, we will know the max pstate state in this socket.
   //
   LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
-  *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal);
+  *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + (UINT32) (((CPB_CTRL_REGISTER *) &PciReg)->NumBoostStates);
 
   return (AGESA_SUCCESS);
 }
@@ -325,25 +374,44 @@ F14GetPstateRegisterInfo (
   IN       AMD_CONFIG_PARAMS   *StdHeader
   )
 {
-  UINT64              MsrRegister;
+  UINT64              LocalMsrReg;
+  UINT32              LocalPciReg;
+  PCI_ADDR            PciAddress;
+  CPU_LOGICAL_ID      CpuFamilyRevision;
 
   ASSERT (PState < NM_PS_REG);
 
   // Read PSTATE MSRs
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrReg, StdHeader);
+
+  *SwPstateNumber = PState;
 
-  if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+  if (((PSTATE_MSR *) &LocalMsrReg)->PsEnable == 1) {
     // PState enable = bit 63
     *PStateEnabled = TRUE;
+    // For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
+    GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+    if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+      // ON_Ax & ON_Bx don't have boosted p-state function
+      PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciReg, StdHeader); // D18F4x15C
+      //
+      // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
+      //
+      if (PState < ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates) {
+        *PStateEnabled = FALSE;
+      } else {
+        *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates;
+      }
+    }
   } else {
     *PStateEnabled = FALSE;
   }
 
-  *SwPstateNumber = PState;
   // Bits 39:32 (high 32 bits [7:0])
-  *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
+  *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddValue;
   // Bits 41:40 (high 32 bits [9:8])
-  *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
+  *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddDiv;
 
   return (AGESA_SUCCESS);
 }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
index 249a3bcc80..6eec83f63d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU/F14
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 46836 $   @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
  *
  */
 /*
@@ -50,10 +50,10 @@
  */
 #include "AGESA.h"
 #include "amdlib.h"
-#include "cpuCacheInit.h"
 #include "cpuRegisters.h"
 #include "cpuFamilyTranslation.h"
 #include "cpuF14PowerMgmt.h"
+#include "cpuF14SoftwareThermal.h"
 #include "Filecode.h"
 #define FILECODE PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE
 
@@ -95,18 +95,33 @@ F14PmThermalInit (
   IN       AMD_CONFIG_PARAMS     *StdHeader
   )
 {
-  UINT32    PciRegister;
+  UINT32    NbCaps;
+  UINT32    LocalPciRegister;
   PCI_ADDR  PciAddress;
+  CPU_LOGICAL_ID CpuFamilyRevision;
 
   PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-  if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) {
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
+  if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) {
     PciAddress.AddressValue = HTC_PCI_ADDR;
-    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-    if (((HTC_REGISTER *) &PciRegister)->HtcTmpLmt != 0) {
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
       // Enable HTC
-      ((HTC_REGISTER *) &PciRegister)->HtcEn = 1;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
     }
   }
+
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
+    PciAddress.AddressValue = LHTC_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) {
+      if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) {
+        // Enable local HTC
+        ((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1;
+      }
+    }
+    LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  }
 }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
index f6a13e59fe..1ddcb15c96 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
@@ -84,6 +84,38 @@ F14ConvertEnabledBitsIntoCount (
   IN       UINT8 EnabledCores
   );
 
+BOOLEAN
+F14GetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F14IsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F14GetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT8
+F14GetNumberOfCoresForBrandstring (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
 
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
@@ -132,12 +164,12 @@ F14DisablePstate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   ASSERT (StateNumber < NM_PS_REG);
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
-  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ((PSTATE_MSR *) &MsrReg)->PsEnable = 0;
+  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
   return (AGESA_SUCCESS);
 }
 
@@ -162,18 +194,18 @@ F14TransitionPstate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
 
   ASSERT (StateNumber < NM_PS_REG);
-  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
-  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
-  LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
-  ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
-  LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+  LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader);
+  ((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader);
   if (WaitForTransition) {
     do {
-      LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
-    } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
+      LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
+    } while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber);
   }
   return (AGESA_SUCCESS);
 }
@@ -198,15 +230,15 @@ F14GetTscRate (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT64 MsrRegister;
+  UINT64 MsrReg;
   PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
 
   FamilyServices = NULL;
-  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
   ASSERT (FamilyServices != NULL);
 
-  LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
-  if ((MsrRegister & 0x01000000) != 0) {
+  LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader);
+  if ((MsrReg & 0x01000000) != 0) {
     return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
   } else {
     return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
@@ -232,15 +264,15 @@ F14GetCurrentNbFrequency (
   IN       AMD_CONFIG_PARAMS *StdHeader
   )
 {
-  UINT32 PciRegister;
+  UINT32 PciReg;
   UINT32 MainPllFid;
   PCI_ADDR PciAddress;
 
   PciAddress.AddressValue = CPTC0_PCI_ADDR;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
 
-  if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
-    MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
+  if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
+    MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
   } else {
     MainPllFid = 0;
   }
@@ -283,7 +315,7 @@ F14GetNbPstateInfo (
   )
 {
   UINT32   NbVid;
-  UINT32   PciRegister;
+  UINT32   PciReg;
   UINT32   MainPllFreq;
   BOOLEAN  PstateIsValid;
 
@@ -294,15 +326,15 @@ F14GetNbPstateInfo (
     if (NbPstate == 0) {
       PciAddress->Address.Function = FUNC_3;
       PciAddress->Address.Register = CPTC2_REG;
-      LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
-      *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0NclkDiv;
-      NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid;
+      LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
+      *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0NclkDiv;
+      NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid;
     } else {
       PciAddress->Address.Function = FUNC_6;
       PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG;
-      LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
-      *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1NclkDiv;
-      NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1Vid;
+      LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
+      *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1NclkDiv;
+      NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1Vid;
     }
     *VoltageInuV = (1550000 - (12500 * NbVid));
     PstateIsValid = TRUE;
@@ -330,12 +362,12 @@ F14IsNbPstateEnabled (
   IN       AMD_CONFIG_PARAMS      *StdHeader
   )
 {
-  UINT32         PciRegister;
+  UINT32         PciReg;
   PCI_ADDR       PciAddress;
 
   PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-  return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPsCap == 1));
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+  return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPsCap == 1));
 }
 
 /*---------------------------------------------------------------------------------------*/
@@ -391,7 +423,7 @@ F14LaunchApCore (
   )
 {
   UINT32    NodeRelativeCoreNum;
-  UINT32    PciRegister;
+  UINT32    PciReg;
   PCI_ADDR  PciAddress;
   BOOLEAN   LaunchFlag;
 
@@ -403,10 +435,10 @@ F14LaunchApCore (
   switch (NodeRelativeCoreNum) {
   case 1:
     PciAddress.Address.Register = HT_TRANS_CTRL;
-    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-    if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
-      PciRegister |= HT_TRANS_CTRL_CPU1_EN;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+    if ((PciReg & HT_TRANS_CTRL_CPU1_EN) == 0) {
+      PciReg |= HT_TRANS_CTRL_CPU1_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
       LaunchFlag = TRUE;
     } else {
       LaunchFlag = FALSE;
@@ -471,7 +503,7 @@ F14GetProcIddMax (
 {
   UINT32       IddDiv;
   UINT32       CmpCap;
-  UINT32       PciRegister;
+  UINT32       PciReg;
   UINT32       MsrAddress;
   UINT64       PstateMsr;
   BOOLEAN      IsPstateEnabled;
@@ -486,8 +518,8 @@ F14GetProcIddMax (
   LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
   if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
     PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
-    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
-    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCap);
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // F3xE8
+    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciReg)->CmpCap);
     CmpCap++;
 
     switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
index 50c773516a..8fe1080176 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
@@ -67,6 +67,14 @@
  *----------------------------------------------------------------------------------------
  */
 
+VOID
+GetF14WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F14WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h
index bfbbf9b770..677cd79a20 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h
@@ -70,37 +70,37 @@
 
 // CPU_LOGICAL_ID.Family equates
 // Family 10h equates
-#define AMD_FAMILY_10_RB  0x0000000000000001
-#define AMD_FAMILY_10_BL  0x0000000000000002
-#define AMD_FAMILY_10_DA  0x0000000000000004
-#define AMD_FAMILY_10_HY  0x0000000000000008
-#define AMD_FAMILY_10_PH  0x0000000000000010
+#define AMD_FAMILY_10_RB  0x0000000000000001ull
+#define AMD_FAMILY_10_BL  0x0000000000000002ull
+#define AMD_FAMILY_10_DA  0x0000000000000004ull
+#define AMD_FAMILY_10_HY  0x0000000000000008ull
+#define AMD_FAMILY_10_PH  0x0000000000000010ull
 #define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
 
 #define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)
 #define AMD_FAMILY_GH    (AMD_FAMILY_10)
 
 // Family 12h equates
-#define AMD_FAMILY_12_LN  0x0000000000000020
+#define AMD_FAMILY_12_LN  0x0000000000000020ull
 #define AMD_FAMILY_12   (AMD_FAMILY_12_LN)
 #define AMD_FAMILY_LN   (AMD_FAMILY_12_LN)
 
 // Family 14h equates
-#define AMD_FAMILY_14_ON  0x0000000000000040
+#define AMD_FAMILY_14_ON  0x0000000000000040ull
 #define AMD_FAMILY_14   (AMD_FAMILY_14_ON)
 #define AMD_FAMILY_ON   (AMD_FAMILY_14_ON)
 
 // Family 15h equates
-#define AMD_FAMILY_15_OR  0x0000000000000080
+#define AMD_FAMILY_15_OR  0x0000000000000100ull
 #define AMD_FAMILY_15     (AMD_FAMILY_15_OR)
 #define AMD_FAMILY_OR     (AMD_FAMILY_15_OR)
 
 // Family 16h equates
-#define AMD_FAMILY_16   0x0000000000000100
-#define AMD_FAMILY_WF   (AMD_FAMILY_16)
+#define AMD_FAMILY_16     0x0000000000000800ull
+#define AMD_FAMILY_WF     (AMD_FAMILY_16)
 
 // Family Unknown
-#define AMD_FAMILY_UNKNOWN 0x8000000000000000
+#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
 
 // Family Group equates
 #define AMD_FAMILY_GE_12   (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16)
@@ -108,27 +108,27 @@
 // Family 10h CPU_LOGICAL_ID.Revision equates
 // -------------------------------------
   // Family 10h RB steppings
-#define AMD_F10_RB_C0      0x0000000000000001
-#define AMD_F10_RB_C1      0x0000000000000002
-#define AMD_F10_RB_C2      0x0000000000000004
-#define AMD_F10_RB_C3      0x0000000000000008
+#define AMD_F10_RB_C0      0x0000000000000001ull
+#define AMD_F10_RB_C1      0x0000000000000002ull
+#define AMD_F10_RB_C2      0x0000000000000004ull
+#define AMD_F10_RB_C3      0x0000000000000008ull
   // Family 10h BL steppings
-#define AMD_F10_BL_C2      0x0000000000000010
-#define AMD_F10_BL_C3      0x0000000000000020
+#define AMD_F10_BL_C2      0x0000000000000010ull
+#define AMD_F10_BL_C3      0x0000000000000020ull
   // Family 10h DA steppings
-#define AMD_F10_DA_C2      0x0000000000000040
-#define AMD_F10_DA_C3      0x0000000000000080
+#define AMD_F10_DA_C2      0x0000000000000040ull
+#define AMD_F10_DA_C3      0x0000000000000080ull
   // Family 10h HY SCM steppings
-#define AMD_F10_HY_SCM_D0  0x0000000000000100
-#define AMD_F10_HY_SCM_D1  0x0000000000000400
+#define AMD_F10_HY_SCM_D0  0x0000000000000100ull
+#define AMD_F10_HY_SCM_D1  0x0000000000000400ull
   // Family 10h HY MCM steppings
-#define AMD_F10_HY_MCM_D0  0x0000000000000200
-#define AMD_F10_HY_MCM_D1  0x0000000000000800
+#define AMD_F10_HY_MCM_D0  0x0000000000000200ull
+#define AMD_F10_HY_MCM_D1  0x0000000000000800ull
   // Family 10h PH steppings
-#define AMD_F10_PH_E0      0x0000000000001000
+#define AMD_F10_PH_E0      0x0000000000001000ull
 
   // Family 10h Unknown stepping
-#define AMD_F10_UNKNOWN    0x8000000000000000
+#define AMD_F10_UNKNOWN    0x8000000000000000ull
 
   // Family 10h Miscellaneous equates
 #define AMD_F10_C0 (AMD_F10_RB_C0)
@@ -168,43 +168,58 @@
 // -------------------------------------
 
   // Family 12h LN steppings
-#define AMD_F12_LN_A0    0x0000000000000001
-#define AMD_F12_LN_A1    0x0000000000000002
-#define AMD_F12_LN_B0    0x0000000000000004
+#define AMD_F12_LN_A0    0x0000000000000001ull
+#define AMD_F12_LN_A1    0x0000000000000002ull
+#define AMD_F12_LN_B0    0x0000000000000004ull
   // Family 12h Unknown stepping
-#define AMD_F12_UNKNOWN  0x8000000000000000
+#define AMD_F12_UNKNOWN  0x8000000000000000ull
 
 #define AMD_F12_LN_Ax    (AMD_F12_LN_A0 | AMD_F12_LN_A1)
 #define AMD_F12_LN_Bx    (AMD_F12_LN_B0)
 
-#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
+#define AMD_F12_ALL      (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
 
 // Family 14h CPU_LOGICAL_ID.Revision equates
 // -------------------------------------
 
   // Family 14h ON steppings
-#define AMD_F14_ON_A0    0x0000000000000001
-#define AMD_F14_ON_A1    0x0000000000000002
-#define AMD_F14_ON_B0    0x0000000000000004
+#define AMD_F14_ON_A0    0x0000000000000001ull
+#define AMD_F14_ON_A1    0x0000000000000002ull
+#define AMD_F14_ON_B0    0x0000000000000004ull
+#define AMD_F14_ON_C0    0x0000000000000008ull
+  // Family 14h KR steppings
+#define AMD_F14_KR_A0    0x0000000000000100ull
+#define AMD_F14_KR_A1    0x0000000000000200ull
+#define AMD_F14_KR_B0    0x0000000000000400ull
   // Family 14h Unknown stepping
-#define AMD_F14_UNKNOWN  0x8000000000000000
+#define AMD_F14_UNKNOWN  0x8000000000000000ull
 
 #define AMD_F14_ON_Ax    (AMD_F14_ON_A0 | AMD_F14_ON_A1)
 #define AMD_F14_ON_Bx    (AMD_F14_ON_B0)
+#define AMD_F14_ON_Cx    (AMD_F14_ON_C0)
+#define AMD_F14_ON_ALL   (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
 
-#define AMD_F14_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_UNKNOWN)
+#define AMD_F14_ALL      (AMD_F14_ON_ALL | AMD_F14_UNKNOWN)
 
 // Family 15h CPU_LOGICAL_ID.Revision equates
 // -------------------------------------
 
   // Family 15h OROCHI steppings
-#define AMD_F15_OR_A0    0x0000000000000001
+#define AMD_F15_OR_A0    0x0000000000000001ull
+#define AMD_F15_OR_A1    0x0000000000000002ull
+#define AMD_F15_OR_B0    0x0000000000000004ull
+  // Family 15h TN steppings
+#define AMD_F15_TN_A0    0x0000000000000100ull
   // Family 15h Unknown stepping
-#define AMD_F15_UNKNOWN  0x8000000000000000
+#define AMD_F15_UNKNOWN  0x8000000000000000ull
 
-#define AMD_F15_OR_Ax    (AMD_F15_OR_A0)
+#define AMD_F15_OR_Ax    (AMD_F15_OR_A0 | AMD_F15_OR_A1)
+#define AMD_F15_OR_Bx    AMD_F15_OR_B0
+#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx)
+#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
+#define AMD_F15_OR_ALL   (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
 
-#define AMD_F15_ALL (AMD_F15_OR_Ax | AMD_F15_UNKNOWN)
+#define AMD_F15_ALL      (AMD_F15_OR_ALL | AMD_F15_UNKNOWN)
 
 // Family 16h CPU_LOGICAL_ID.Revision equates
 // TBD
author	efdesign98 <efdesign98@gmail.com>	2011-08-04 12:09:17 -0600
committer	Patrick Georgi <patrick@georgi-clan.de>	2011-08-06 18:06:18 +0200
commit	84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch)
tree	57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/CPU/Family
parent	0df0e14fb5b613e76ff022359c55d5df5633b40f (diff)