diff options
author | Joe Moore <awokd@danwin1210.me> | 2019-10-21 00:32:00 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:23:38 +0000 |
commit | a0e1e596f894416c9db9eefe5b742cb4fad23a00 (patch) | |
tree | 7c8923de83e25e74637b9d128ea7a715287c0ec8 /src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1 | |
parent | 2c08ea7cfcb24240e41ad0f75be35f9e2967b3d1 (diff) |
vc/amd/agesa: Remove fam12
With removal of Torpedo mainboard, this code is no longer
necessary. Will resolve some unique Coverity issues.
Change-Id: I2927245c426566a8f80863a109d015ebf6176803
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1')
6 files changed, 0 insertions, 1410 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h deleted file mode 100644 index 9b1891762b..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h +++ /dev/null @@ -1,51 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe training library - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _GNBPCIETRAININGV1_H_ -#define _GNBPCIETRAININGV1_H_ - -#include "PcieTraining.h" -#include "PcieWorkarounds.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc deleted file mode 100644 index 5b6b04d092..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += PcieTraining.c -libagesa-y += PcieWorkarounds.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c deleted file mode 100644 index 48d59afbdd..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ /dev/null @@ -1,864 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link training - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbPcieInitLibV1.h" -#include "PcieWorkarounds.h" -#include "PcieTraining.h" -#include "GnbRegistersLN.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -PcieSetResetStateOnEngines ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingCheckResetDuration ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingDeassertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingBrokenLine ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingGen2Fail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -/* - VOID -STATIC -PcieTrainingDebugDumpPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ); -*/ - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set link State - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] State State to set - * @param[in] UpdateTimeStamp Update time stamp - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingSetPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN UINT8 State, - IN BOOLEAN UpdateTimeStamp, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - CurrentEngine->Type.Port.State = State; - if (UpdateTimeStamp) { - TimeStamp = PcieTimerGetTimeStamp (Pcie); - CurrentEngine->Type.Port.TimeStamp = TimeStamp; - } - GNB_DEBUG_CODE ( - PcieTrainingDebugDumpPortState (CurrentEngine, Pcie) - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Set state for all engines connected to same reset ID - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Pointer to Reset Id - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieSetResetStateOnEngines ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 ResetId; - ResetId = *(UINT8 *)Buffer; - if (Engine->Type.Port.PortData.ResetId == ResetId) { - PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Assert GPIO port reset. - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingAssertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SLOT_RESET_INFO ResetInfo; - ResetInfo.ResetControl = AssertSlotReset; - ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; - LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); - AgesaPcieSlotResetControl (0, &ResetInfo); - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieSetResetStateOnEngines, - (VOID *)&CurrentEngine->Type.Port.PortData.ResetId, - Pcie - ); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Check for reset duration - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingCheckResetDuration ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) { - PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Deassert GPIO port reset. - * - * Transition to LinkStateResetDuration state - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Platform configuration - * - */ -VOID -PcieTrainingDeassertReset ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SLOT_RESET_INFO ResetInfo; - ResetInfo.ResetControl = DeassertSlotReset; - ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; - LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); - AgesaPcieSlotResetControl (0, &ResetInfo); - PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check for after reset deassertion timeout - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCheckResetTimeout ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) { - PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Release training - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingRelease ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkTrainingState; - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (CurrentEngine), - WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), - D0F0xE4_WRAP_0800_HoldTraining_OFFSET, - D0F0xE4_WRAP_0800_HoldTraining_WIDTH, - 0, - FALSE, - Pcie - ); - if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - LinkTrainingState = LinkStateCompliance; - } else { - LinkTrainingState = LinkStateDetectPresence; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Detect presence of any EP on the link - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingDetectPresence ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[4]; - UINT32 TimeStamp; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); - if (LinkHwStateHistory[0] > 4) { - PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); - return; - } - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) { - PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); - } -} - -UINT8 FailPattern1 [] = {0x2a, 0x6}; -UINT8 FailPattern2 [] = {0x2a, 0x9}; - -/*----------------------------------------------------------------------------------------*/ -/** - * Detect Link State - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingDetectLinkState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkHwStateHistory[16]; - UINT32 TimeStamp; - UINT8 LinkTrainingState; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); - if (LinkHwStateHistory[0] == 0x10) { - PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie); - return; - }; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) { - LinkTrainingState = LinkStateTrainingFail; - PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie); - if (LinkHwStateHistory[0] == 0x7) { - LinkTrainingState = LinkStateCompliance; - } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) { - LinkTrainingState = LinkStateBrokenLane; - } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) { - LinkTrainingState = LinkStateGen2Fail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Broken Lane - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -PcieTrainingBrokenLine ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 CurrentLinkWidth; - UINT8 LinkTrainingState; - CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie); - if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) { - CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY; - PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie); - LinkTrainingState = LinkStateResetAssert; - PutEventLog ( - AGESA_WARNING, - GNB_EVENT_BROKEN_LANE_RECOVERY, - CurrentEngine->Type.Port.Address.AddressValue, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } else { - LinkTrainingState = LinkStateGen2Fail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link fail because device does not support Gen2 - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -PcieTrainingGen2Fail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT8 LinkTrainingState; - if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) { - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0); - CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1; - PcieLinkSafeMode (CurrentEngine, Pcie); - LinkTrainingState = LinkStateResetAssert; - PutEventLog ( - AGESA_WARNING, - GNB_EVENT_BROKEN_LANE_RECOVERY, - CurrentEngine->Type.Port.Address.AddressValue, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } else { - LinkTrainingState = LinkStateTrainingFail; - } - PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Link in L0 - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieCheckLinkL0 ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie); -} -/*----------------------------------------------------------------------------------------*/ -/** - * Check if link fail because device does not support Gen X - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCheckVcoNegotiation ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - DxF0x128_STRUCT DxF0x128; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxF0x128_ADDRESS, AccessWidth32, &DxF0x128, GnbLibGetHeader (Pcie)); - if (DxF0x128.Field.VcNegotiationPending == 0) { - UINT16 NumberOfPhyLane; - NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine); - if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) { - // Limit exposure of workaround to x8 and x16 port. - PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie); - } else { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); - } - return; - } - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) { - PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if for GFX workaround condition - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingGfxWorkaround ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - UINT32 TimeStamp; - GFX_WORKAROUND_STATUS GfxWorkaroundStatus; - TimeStamp = PcieTimerGetTimeStamp (Pcie); - - GfxWorkaroundStatus = PcieGfxCardWorkaround (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie)); - switch (GfxWorkaroundStatus) { - case GFX_WORKAROUND_DEVICE_NOT_READY: - if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 2000) { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); - } - break; - case GFX_WORKAROUND_SUCCESS: - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); - break; - case GFX_WORKAROUND_RESET_DEVICE: - if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) { - CurrentEngine->Type.Port.GfxWrkRetryCount++; - PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie); - } else { - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); - } - break; - default: - ASSERT (FALSE); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Retrain link - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingRetrainLink ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PciePortRegisterWriteField ( - CurrentEngine, - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcReconfigNow_OFFSET, - DxF0xE4_xA2_LcReconfigNow_WIDTH, - 1, - FALSE, - Pcie - ); - PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Training fail on this port - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingFail ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Links training success - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingSuccess ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Links in compliance - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCompliance ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0); - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * PCie EP not present - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingNotPresent ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) { - } else { - PcieRegisterWriteField ( - PcieConfigGetParentWrapper (CurrentEngine), - WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), - D0F0xE4_WRAP_0800_HoldTraining_OFFSET, - D0F0xE4_WRAP_0800_HoldTraining_WIDTH, - 1, - FALSE, - Pcie - ); - } - PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Final state. Port training completed. - * - * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ -VOID -STATIC -PcieTrainingCompleted ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Training state handling - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Indicate if engine in non final state - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PcieTrainingPortCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - BOOLEAN *TrainingComplete; - TrainingComplete = (BOOLEAN *) Buffer; - if (Engine->Type.Port.State < Pcie->TrainingExitState) { - *TrainingComplete = FALSE; - } else { - return; - } - switch (Engine->Type.Port.State) { - case LinkStateResetAssert: - PcieTrainingAssertReset (Engine, Pcie); - break; - case LinkStateResetDuration: - PcieTrainingCheckResetDuration (Engine, Pcie); - break; - case LinkStateResetExit: - PcieTrainingDeassertReset (Engine, Pcie); - break; - case LinkTrainingResetTimeout: - PcieTrainingCheckResetTimeout (Engine, Pcie); - break; - case LinkStateReleaseTraining: - PcieTrainingRelease (Engine, Pcie); - break; - case LinkStateDetectPresence: - PcieTrainingDetectPresence (Engine, Pcie); - break; - case LinkStateDetecting: - PcieTrainingDetectLinkState (Engine, Pcie); - break; - case LinkStateBrokenLane: - PcieTrainingBrokenLine (Engine, Pcie); - break; - case LinkStateGen2Fail: - PcieTrainingGen2Fail (Engine, Pcie); - break; - case LinkStateL0: - PcieCheckLinkL0 (Engine, Pcie); - break; - case LinkStateVcoNegotiation: - PcieTrainingCheckVcoNegotiation (Engine, Pcie); - break; - case LinkStateRetrain: - PcieTrainingRetrainLink (Engine, Pcie); - break; - case LinkStateTrainingFail: - PcieTrainingFail (Engine, Pcie); - break; - case LinkStateGfxWorkaround: - PcieTrainingGfxWorkaround (Engine, Pcie); - break; - case LinkStateTrainingSuccess: - PcieTrainingSuccess (Engine, Pcie); - break; - case LinkStateCompliance: - PcieTrainingCompliance (Engine, Pcie); - break; - case LinkStateDeviceNotPresent: - PcieTrainingNotPresent (Engine, Pcie); - break; - case LinkStateTrainingCompleted: - PcieTrainingCompleted (Engine, Pcie); - break; - default: - break; - } - -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Main link training procedure - * - * Port end up in three possible state LinkStateTrainingNotPresent/LinkStateCompliance/ - * LinkStateTrainingSuccess - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PcieTraining ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - BOOLEAN TrainingComplete; - Status = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n"); - do { - TrainingComplete = TRUE; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieTrainingPortCallback, - &TrainingComplete, - Pcie - ); - } while (!TrainingComplete); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump port state on state transition - * - * - * @param[in] CurrentEngine Pointer to engine config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -/* -VOID -STATIC -PcieTrainingDebugDumpPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - IDS_HDT_CONSOLE (PCIE_MISC, " Port %d:%d:%d State [%s] Time Stamp [%d]\n", - CurrentEngine->Type.Port.Address.Address.Bus, - CurrentEngine->Type.Port.Address.Address.Device, - CurrentEngine->Type.Port.Address.Address.Function, - (CurrentEngine->Type.Port.State == LinkStateTrainingFail) ? "LinkStateTrainingFail " : ( - (CurrentEngine->Type.Port.State == LinkStateTrainingSuccess) ? "LinkStateTrainingSuccess " : ( - (CurrentEngine->Type.Port.State == LinkStateCompliance) ? "LinkStateCompliance " : ( - (CurrentEngine->Type.Port.State == LinkStateDeviceNotPresent) ? "LinkStateDeviceNotPresent" : ( - (CurrentEngine->Type.Port.State == LinkStateResetAssert) ? "LinkStateResetAssert " : ( - (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetDuration " : ( - (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetExit " : ( - (CurrentEngine->Type.Port.State == LinkTrainingResetTimeout) ? "LinkTrainingResetTimeout " : ( - (CurrentEngine->Type.Port.State == LinkStateReleaseTraining) ? "LinkStateReleaseTraining " : ( - (CurrentEngine->Type.Port.State == LinkStateDetectPresence) ? "LinkStateDetectPresence " : ( - (CurrentEngine->Type.Port.State == LinkStateDetecting) ? "LinkStateDetecting " : ( - (CurrentEngine->Type.Port.State == LinkStateBrokenLane) ? "LinkStateBrokenLane " : ( - (CurrentEngine->Type.Port.State == LinkStateGen2Fail) ? "LinkStateGen2Fail " : ( - (CurrentEngine->Type.Port.State == LinkStateL0) ? "LinkStateL0 " : ( - (CurrentEngine->Type.Port.State == LinkStateVcoNegotiation) ? "LinkStateVcoNegotiation " : ( - (CurrentEngine->Type.Port.State == LinkStateGfxWorkaround) ? "LinkStateGfxWorkaround " : ( - (CurrentEngine->Type.Port.State == LinkStateTrainingCompleted) ? "LinkStateTrainingComplete" : ( - (CurrentEngine->Type.Port.State == LinkStateRetrain) ? "LinkStateRetrain " : ( - (CurrentEngine->Type.Port.State == LinkStateResetExit) ? "LinkStateResetExit " : "Unknown")))))))))))))))))), - CurrentEngine->Type.Port.TimeStamp - ); -} -*/ diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h deleted file mode 100644 index 302c78adb4..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe link training - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIETRAINING_H_ -#define _PCIETRAINING_H_ - - -AGESA_STATUS -PcieTraining ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieTrainingSetPortState ( - IN PCIe_ENGINE_CONFIG *CurrentEngine, - IN UINT8 State, - IN BOOLEAN UpdateTimeStamp, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c deleted file mode 100644 index 891463189e..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +++ /dev/null @@ -1,375 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various workarounds - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 48452 $ @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "GnbRegistersLN.h" -#include "PcieWorkarounds.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieConfigureBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieFreeBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -GFX_WORKAROUND_STATUS -PcieDeskewWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -GFX_WORKAROUND_STATUS -PcieNvWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieProgramCpuMmio ( - OUT UINT32 *SaveValues, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -PcieRestoreCpuMmio ( - IN UINT32 *RestoreValues, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -PcieIsDeskewCardDetected ( - IN UINT16 DeviceId - ); - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * ATI RV370/RV380 card workaround - * - * - * - * @param[in] Port PCI addreses of the port - * @param[in] StdHeader Standard configuration header - * @retval GFX_WORKAROUND_STATUS Return the GFX Card Workaround status - */ -GFX_WORKAROUND_STATUS -PcieGfxCardWorkaround ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - GFX_WORKAROUND_STATUS Status; - UINT16 DeviceId; - UINT16 VendorId; - UINT8 DevClassCode; - UINT32 SaveValueData[2]; - PCI_ADDR Ep; - - Status = GFX_WORKAROUND_SUCCESS; - - Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0); - if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) { - GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader); - Status = GFX_WORKAROUND_DEVICE_NOT_READY; - if (DeviceId != 0xffff) { - GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader); - if (VendorId != 0xffff) { - GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader); - Status = GFX_WORKAROUND_SUCCESS; - if (DevClassCode == 3) { - PcieProgramCpuMmio (SaveValueData, StdHeader); - if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) { - Status = PcieDeskewWorkaround (Ep, StdHeader); - } else if (VendorId == 0x10DE) { - Status = PcieNvWorkaround (Ep, StdHeader); - } - PcieRestoreCpuMmio (SaveValueData, StdHeader); - } - } - } - PcieFreeBridgeResources (Port, StdHeader); - } - return Status; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * RV370/RV380 Deskew workaround - * - * - * - * @param[in] Device Pcie Address of ATI RV370/RV380 card. - * @param[in] StdHeader Standard configuration header - */ -GFX_WORKAROUND_STATUS -PcieDeskewWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN MmioBase; - UINT16 MmioData1; - UINT32 MmioData2; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return GFX_WORKAROUND_SUCCESS; - } - GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~(UINT32)BIT1, BIT1, StdHeader); - GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader); - GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader); - if (MmioData1 == 0xb700) { - GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader); - GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader); - if (MmioData2 == 0x13) { - GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader); - if (MmioData2 & BIT8) { - return GFX_WORKAROUND_RESET_DEVICE; - } - } - } - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~(UINT32)BIT1, 0x0, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader); - - return GFX_WORKAROUND_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * NV43 card workaround (lost SSID) - * - * - * - * @param[in] Device Pcie Address of NV43 card. - * @param[in] StdHeader Standard configuration header - */ -GFX_WORKAROUND_STATUS -PcieNvWorkaround ( - IN PCI_ADDR Device, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 DeviceSSID; - UINTN MmioBase; - UINT32 MmioData3; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return GFX_WORKAROUND_SUCCESS; - } - GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader); - GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader); - GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader); - if (DeviceSSID != MmioData3) { - GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader); - } - GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader); - return GFX_WORKAROUND_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate temporary resources for Pcie P2P bridge - * - * - * - * @param[in] Port Pci Address of Port to initialize. - * @param[in] StdHeader Standard configuration header - */ -AGESA_STATUS -PcieConfigureBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - UINT32 MmioBase; - - MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; - if (MmioBase == 0) { - return AGESA_WARNING; - } - Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16); - GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = MmioBase + (MmioBase >> 16); - GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = 0x000fff0; - GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); - Value = 0x2; - GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader); - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Free temporary resources for Pcie P2P bridge - * - * - * - * @param[in] Port Pci Address of Port to clear resource allocation. - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieFreeBridgeResources ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Value; - - Value = 0; - GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader); - GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader); - -} - - -/*----------------------------------------------------------------------------------------*/ -/* - * Save CPU MMIO register - * - * - * - * @param[out] UINT32 SaveValues - * @param[in] StdHeader Standard configuration header - * - */ -VOID -PcieProgramCpuMmio ( - OUT UINT32 *SaveValues, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //Save CPU MMIO Register - GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader); - GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader); - - //Write Temp Pcie MMIO to CPU - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader); - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Restore CPU MMIO register - * - * - * - * @param[in] PCIe_PLATFORM_CONFIG Pcie - * @param[in] StdHeader Standard configuration header - */ -VOID -PcieRestoreCpuMmio ( - IN UINT32 *RestoreValues, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //Restore CPU MMIO Register - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader); - GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader); - -} - -/*----------------------------------------------------------------------------------------*/ -/* - * Check if card required test for deskew workaround - * - * - * - * @param[in] DeviceId Device ID - */ - -BOOLEAN -PcieIsDeskewCardDetected ( - IN UINT16 DeviceId - ) -{ - if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) || - (DeviceId == 0x3E50) || (DeviceId == 0x3E54) || - ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8) == 0x5B60)) { - return TRUE; - } - return FALSE; -} - - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h deleted file mode 100644 index 14bc3350ea..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h +++ /dev/null @@ -1,55 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Various workarounds - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEWORKAROUNDS_H_ -#define _PCIEWORKAROUNDS_H_ - -GFX_WORKAROUND_STATUS -PcieGfxCardWorkaround ( - IN PCI_ADDR Port, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -#endif |