diff options
author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-06-04 10:37:35 -0700 |
---|---|---|
committer | Marc Jones <marcj303@gmail.com> | 2011-06-20 19:08:05 +0200 |
commit | d1cb0eecd130cb4259ce9fedb32ebcd9ada0d4b7 (patch) | |
tree | 26d717ae20d6c61e6c07a5482b1a8811a2bee8c7 /src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h | |
parent | 46b033e8cb30000148104e45753a033ed6d919c1 (diff) |
sb800: move spi prefetch and fast read mode to sb bootblock.
So we don't waste time on the first cbfs scan.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h')
0 files changed, 0 insertions, 0 deletions