diff options
author | Joe Moore <awokd@danwin1210.me> | 2019-10-21 00:32:00 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:23:38 +0000 |
commit | a0e1e596f894416c9db9eefe5b742cb4fad23a00 (patch) | |
tree | 7c8923de83e25e74637b9d128ea7a715287c0ec8 /src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig | |
parent | 2c08ea7cfcb24240e41ad0f75be35f9e2967b3d1 (diff) |
vc/amd/agesa: Remove fam12
With removal of Torpedo mainboard, this code is no longer
necessary. Will resolve some unique Coverity issues.
Change-Id: I2927245c426566a8f80863a109d015ebf6176803
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig')
10 files changed, 0 insertions, 2618 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h deleted file mode 100644 index 8e91224070..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h +++ /dev/null @@ -1,53 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _GNBPCIECONFIG_H_ -#define _GNBPCIECONFIG_H_ - - -#include "PcieConfigData.h" -#include "PcieConfigLib.h" - -#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc deleted file mode 100644 index d9edf85fae..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -libagesa-y += PcieConfigData.c -libagesa-y += PcieConfigLib.c -libagesa-y += PcieInputParser.c -libagesa-y += PcieMapTopology.c diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c deleted file mode 100644 index 62468baafa..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +++ /dev/null @@ -1,528 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49916 $ @e \$Date: 2011-03-30 19:03:54 +0800 (Wed, 30 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "heapManager.h" -#include "OptionGnb.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "PcieMapTopology.h" -#include "PcieInputParser.h" -#include "PcieConfigLib.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -AGESA_STATUS -PcieConfigurationInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -PcieConfigAttachComplexes ( - IN OUT PCIe_COMPLEX_CONFIG *Base, - IN OUT PCIe_COMPLEX_CONFIG *New - ); - -AGESA_STATUS -PcieUpdateConfigurationData ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -STATIC -PcieConfigBuildData ( - IN AMD_EARLY_PARAMS *EarlyParamsPtr, - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -PCIe_COMPLEX_DESCRIPTOR * -PcieConfigProcessUserConfig ( - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Create internal PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Configuration data successfully allocated. - * @retval AGESA_FATAL Configuration data allocation failed. - */ - -AGESA_STATUS -PcieConfigurationInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AMD_EARLY_PARAMS *EarlyParamsPtr; - PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; - AGESA_STATUS Status; - EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader; - - /* FIXME: Intentionally discard qualifier const of - * GnbConfig.PcieComplexList here. - */ - PcieComplexList = PcieConfigProcessUserConfig ( - (PCIe_COMPLEX_DESCRIPTOR *)EarlyParamsPtr->GnbConfig.PcieComplexList, - StdHeader); - - if (PcieComplexList == NULL) { - return AGESA_FATAL; - } - GNB_DEBUG_CODE ( - PcieUserConfigConfigDump (PcieComplexList); - ); - Status = PcieConfigBuildData (EarlyParamsPtr, PcieComplexList, StdHeader); - HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Create internal PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_SUCCESS Configuration data successfully allocated. - * @retval AGESA_FATAL Configuration data allocation failed. - */ - -AGESA_STATUS -STATIC -PcieConfigBuildData ( - IN AMD_EARLY_PARAMS *EarlyParamsPtr, - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCIe_PLATFORM_CONFIG *Pcie; - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor; - UINTN ComplexesDataLength; - UINTN ComplexIndex; - UINTN NumberOfComplexes; - VOID *Buffer; - UINTN Index; - UINT32 NumberOfSockets; - UINT8 SocketId; - PCIe_SILICON_CONFIG *Silicon; - UINTN CurrentComplexesDataLength; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n"); - AgesaStatus = AGESA_SUCCESS; - ComplexesDataLength = 0; - NumberOfSockets = GnbGetNumberOfSockets (StdHeader); - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); - ASSERT (Status == AGESA_SUCCESS); - ComplexesDataLength += CurrentComplexesDataLength; - } - } - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); - Pcie = GnbAllocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - if (Pcie == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - Pcie->StdHeader = (PVOID) (intptr_t) StdHeader; - Pcie->Header.Child = offsetof (PCIe_PLATFORM_CONFIG, ComplexList); - PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY); - Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); - ComplexIndex = 0; - for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) { - if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) { - if (ComplexIndex > MAX_NUMBER_OF_COMPLEXES) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - Pcie->ComplexList[ComplexIndex].Header.Child = (UINT16) ((UINT8 *) Buffer - (UINT8 *) &Pcie->ComplexList[ComplexIndex]); - Pcie->ComplexList[ComplexIndex].Header.Parent = (UINT16) ((UINT8 *) &Pcie->ComplexList[ComplexIndex] - (UINT8 *) Pcie); - PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY); - PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); - Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]); - Silicon->Header.Parent = (UINT16) ((UINT8 *) Silicon - (UINT8 *) &Pcie->ComplexList[ComplexIndex]); - for (Index = 0; Index < NumberOfComplexes; Index++) { - ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index); - if (ComplexDescriptor->SocketId == SocketId) { - Status = PcieMapTopologyOnComplex (ComplexDescriptor, &Pcie->ComplexList[ComplexIndex], Pcie); - Pcie->ComplexList[ComplexIndex].SocketId = SocketId; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (ComplexIndex > 0) { - PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]); - } - } - } - PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); - Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength); - ComplexIndex++; - } - } - Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling; - Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling; - Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime; - Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime; - Pcie->GfxCardWorkaround = GfxWorkaroundEnable; - Pcie->TrainingExitState = LinkStateTrainingCompleted; - Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm; - if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { - Pcie->GfxCardWorkaround = GfxWorkaroundDisable; - } - Pcie->PsppPolicy = EarlyParamsPtr->GnbConfig.PsppPolicy; - IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader); - GNB_DEBUG_CODE ( - PcieConfigDebugDump (Pcie); - ); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate global PCIe configuration data - * - * - * - * @param[in] PcieComplexList User PCIe topology configuration - * @param[out] StdHeader Standard configuration header - * @retval Updated topology configuration - */ -PCIe_COMPLEX_DESCRIPTOR * -PcieConfigProcessUserConfig ( - IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Node0SocketId; - UINT32 Node0SiliconId; - UINTN NumberOfComplexes; - UINTN NumberOfPorts; - UINTN Index; - UINT16 DescriptorLoLane; - UINT16 DescriptorHiLane; - PCIe_COMPLEX_DESCRIPTOR *ResultComplexConfig; - PCIe_COMPLEX_DESCRIPTOR *SbComplexDescriptor; - PCIe_PORT_DESCRIPTOR *SbPortDescriptor; - PCIe_PORT_DESCRIPTOR DefaultSbPortDescriptor; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - AGESA_STATUS Status; - SbPortDescriptor = NULL; - GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader); - Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader); - if (Status == AGESA_UNSUPPORTED) { - return PcieComplexList; - } - if (PcieComplexList == NULL) { - // No complex descriptor for any silicon was provided - // 1. Create complex descriptor - // 2. Create SB port descriptor - // 3. Attach SB descriptor to complex descriptor created in step #1 - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( - AMD_GNB_TEMP_DATA_HANDLE, - sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - SbComplexDescriptor = ResultComplexConfig; - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR)); - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - // Attach post array to complex descriptor - SbComplexDescriptor->PciePortList = SbPortDescriptor; - SbComplexDescriptor->SocketId = Node0SocketId; - SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - } else { - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); - SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId); - if (SbComplexDescriptor == NULL) { - // No complex descriptor for silicon that have SB attached. - // 1. Create complex descriptor. Will be first one in the list - // 2. Create SB port descriptor - // 3. Attach SB descriptor to complex descriptor created in step #1 - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( - AMD_GNB_TEMP_DATA_HANDLE, - (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - SbComplexDescriptor = ResultComplexConfig; - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - // Attach post array to complex descriptor - SbComplexDescriptor->PciePortList = SbPortDescriptor; - SbComplexDescriptor->SocketId = Node0SocketId; - SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; - LibAmdMemCopy ( - (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR), - PcieComplexList, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - StdHeader - ); - - } else { - // Complex descriptor that represent silicon that have SB attached exist - // 1. Determine if complex have descriptor for SB - // 2. Create new descriptor for SB if needed - NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor); - ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer ( - AMD_GNB_TEMP_DATA_HANDLE, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Copy complex descriptor array - LibAmdMemCopy ( - ResultComplexConfig, - PcieComplexList, - NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - StdHeader - ); - if (NumberOfPorts != 0) { - // Copy port descriptor array associated with complex with SB attached - LibAmdMemCopy ( - (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), - SbComplexDescriptor->PciePortList, - NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Update SB complex pointer on in memory list - SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId); - // Attach port descriptor array to complex - SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR)); - for (Index = 0; Index < NumberOfPorts; ++Index) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index); - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) { - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor; - } - } - } - } - if (SbPortDescriptor == NULL) { - // No descriptor that represent SB where found, create new one, will be first one in list - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - // Copy default config info - LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); - // Reattach descriptor list to complex - SbComplexDescriptor->PciePortList = SbPortDescriptor; - } else { - // Move SB descriptor to be first one in array - LibAmdMemCopy ( - (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), - SbPortDescriptor, - sizeof (PCIe_PORT_DESCRIPTOR), - StdHeader - ); - // Disable original SB descriptor - SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine; - //Update pointer to new SB descriptor - SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); - //It is no longer a descriptor that terminates list - SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST); - // Reattach descriptor list to complex - SbComplexDescriptor->PciePortList = SbPortDescriptor; - } - } - } - // Mark descriptor as SB link - SbPortDescriptor->Port.MiscControls.SbLink = 0x1; - return ResultComplexConfig; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Locate global PCIe configuration data - * - * - * - * @param[in] StdHeader Standard configuration header - * @param[out] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Configuration data successfully located - * @retval AGESA_FATAL Configuration can not be located. - */ -AGESA_STATUS -PcieLocateConfigurationData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT PCIe_PLATFORM_CONFIG **Pcie - ) -{ - *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader); - if (*Pcie == NULL) { - IDS_ERROR_TRAP; - return AGESA_FATAL; - } - PcieUpdateConfigurationData (*Pcie); - (*Pcie)->StdHeader = (PVOID) (intptr_t) StdHeader; - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Attache descriptors - * - * - * @param[in] Type Descriptor type - * @param[in,out] Base Base descriptor - * @param[in,out] New New descriptor - */ -VOID -STATIC -PcieConfigAttachDescriptors ( - IN UINT32 Type, - IN OUT PCIe_DESCRIPTOR_HEADER *Base, - IN OUT PCIe_DESCRIPTOR_HEADER *New - ) -{ - PCIe_DESCRIPTOR_HEADER *Left; - PCIe_DESCRIPTOR_HEADER *Right; - - Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base)); - Right = PcieConfigGetChild (Type, New); - Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left); - PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Attach configurations of two GNB to each other. - * - * Function will link all data structure to linked lists - * - * @param[in,out] Base Base complex descriptor - * @param[in,out] New New complex descriptor - */ -VOID -STATIC -PcieConfigAttachComplexes ( - IN OUT PCIe_COMPLEX_CONFIG *Base, - IN OUT PCIe_COMPLEX_CONFIG *New - ) -{ - // Connect Complex - Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base); - PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY); - // Connect Silicon - PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header); - // Connect Wrappers - PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header); - // Connect Engines - PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Update configuration data - * - * Puprouse of this structure to update config data that base on programming of - * other silicon compoments. For instance PCI address of GNB and PCIe ports - * can change by AGESA or external agent - * - * - * @param[in,out] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Configuration data successfully update - * @retval AGESA_FATAL Failt to update configuration - */ -AGESA_STATUS -PcieUpdateConfigurationData ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *Silicon; - PCIe_ENGINE_CONFIG *Engine; - PCI_ADDR NewAddress; - // Update silicon configuration - Silicon = PcieConfigGetChildSilicon (Pcie); - while (Silicon != NULL) { - NewAddress = GnbGetPciAddress (PcieConfigGetParentComplex (Silicon)->SocketId, Silicon->SiliconId, GnbLibGetHeader (Pcie)); - if (Silicon->Address.AddressValue != NewAddress.AddressValue) { - Silicon->Address.AddressValue = NewAddress.AddressValue; - Engine = PcieConfigGetChildEngine (Silicon); - while (Engine != NULL) { - if (PcieConfigIsPcieEngine (Engine)) { - Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus; - } - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB); - } - } - Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); - } - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h deleted file mode 100644 index 6a1b3accab..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECONFIGDATA_H_ -#define _PCIECONFIGDATA_H_ - - -AGESA_STATUS -PcieLocateConfigurationData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT PCIe_PLATFORM_CONFIG **Pcie - ); - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c deleted file mode 100644 index c76b290727..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ /dev/null @@ -1,720 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GnbCommonLib.h" -#include "GnbPcieConfig.h" -#include "PcieMapTopology.h" -#include "PcieInputParser.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * get Master Lane of PCIe port engine - * - * - * - * @param[in] Engine Pointer to engine descriptor - * @retval Master Engine Lane Number - */ -UINT8 -PcieConfigGetPcieEngineMasterLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT8 MasterLane; - ASSERT (PcieConfigIsPcieEngine (Engine)); - if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) { - MasterLane = (UINT8) Engine->Type.Port.StartCoreLane; - } else { - MasterLane = (UINT8) Engine->Type.Port.EndCoreLane; - } - return MasterLane; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of core lanes - * - * - * - * @param[in] Engine Pointer to engine descriptor - * @retval Number of core lane - */ -UINT8 -PcieConfigGetNumberOfCoreLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) { - return 0; - } - return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable engine - * - * - * - * @param[in] Engine Pointer to engine config descriptor - */ -VOID -PcieConfigDisableEngine ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (PcieConfigIsSbPcieEngine (Engine)) { - return; - } - PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Disable all engines on wrapper - * - * - * - * @param[in] EngineTypeMask Engine type bitmap. - * @param[in] Wrapper Pointer to wrapper config descriptor - */ -VOID -PcieConfigDisableAllEngines ( - IN UINTN EngineTypeMask, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) { - PcieConfigDisableEngine (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get engine PHY lanes bitmap - * - * - * - * @param[in] Engine Pointer to engine config descriptor - */ -UINT32 -PcieConfigGetEnginePhyLaneBitMap ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - UINT32 LaneBitMap; - LaneBitMap = 0; - if (PcieLibIsEngineAllocated (Engine)) { - LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane); - } - return LaneBitMap; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of phy lanes - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @retval Number of Phy lane - */ -UINT8 -PcieConfigGetNumberOfPhyLane ( - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) { - return 0; - } - if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { - return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1); - } else { - return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get port configuration signature for given wrapper and core - * - * Support for unify register access through index/data pair on GNB - * - * @param[in] Wrapper Pointer to wrapper config descriptor - * @param[in] CoreId Core ID - * @retval Configuration Signature - */ -UINT64 -PcieConfigGetConfigurationSignature ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId - ) -{ - UINT64 ConfigurationSignature; - PCIe_ENGINE_CONFIG *EngineList; - ConfigurationSignature = 0; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (EngineList->Type.Port.CoreId == CoreId) { - ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - return ConfigurationSignature; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check Port Status - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] PortStatus Check if status asserted for port - * @retval TRUE if status asserted - */ -BOOLEAN -PcieConfigCheckPortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 PortStatus - ) -{ - return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set/Reset port status - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in] SetStatus SetStatus - * @param[in] ResetStatus ResetStatus - * - */ -UINT32 -PcieConfigUpdatePortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 SetStatus, - IN UINT32 ResetStatus - ) -{ - Engine->InitStatus |= SetStatus; - Engine->InitStatus &= (~ResetStatus); - return Engine->InitStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all descriptor of specific type - * - * - * @param[in] DescriptorFlags Descriptor flags - * @param[in] TerminateFlags terminate flags - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieConfigRunProcForAllDescriptors ( - IN UINT32 InDescriptorFlags, - IN UINT32 OutDescriptorFlags, - IN UINT32 TerminationFlags, - IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_DESCRIPTOR_HEADER *Descriptor; - - AgesaStatus = AGESA_SUCCESS; - Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header); - while (Descriptor != NULL) { - if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) { - Status = Callback (Descriptor, Buffer, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags); - } - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all wrappers in topology - * - * - * @param[in] DescriptorFlags Wrapper Flags - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -AGESA_STATUS -PcieConfigRunProcForAllWrappers ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_WRAPPER_CONFIG *Wrapper; - - AgesaStatus = AGESA_SUCCESS; - Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header); - while (Wrapper != NULL) { - if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { - if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) { - Status = Callback (Wrapper, Buffer, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } - } - Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY); - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Execute callback on all engine in topology - * - * - * @param[in] DescriptorFlags Engine flags. - * @param[in] Callback Pointer to callback function - * @param[in, out] Buffer Pointer to buffer to pass information to callback - * @param[in] Pcie Pointer to global PCIe configuration - */ - -VOID -PcieConfigRunProcForAllEngines ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - - PCIe_ENGINE_CONFIG *Engine; - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header); - while (Engine != NULL) { - if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { - if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) { - if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) { - Callback (Engine, Buffer, Pcie); - } - } - } - Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get parent descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetParent ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Parent != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get child descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetChild ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Child != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get peer descriptor of specific type - * - * - * @param[in] Type Descriptor type - * @param[in] Descriptor Pointer to buffer to pass information to callback - */ -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetPeer ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ) -{ - while ((Descriptor->DescriptorFlags & Type) == 0) { - if (Descriptor->Peer != 0) { - Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer); - } else { - return NULL; - } - } - return Descriptor; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump engine configuration - * - * - * @param[in] EngineList Engine Configuration - */ -VOID -PcieConfigEngineDebugDump ( - IN PCIe_ENGINE_CONFIG *EngineList - ) -{ - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n Start Phy Lane - %d\n End Phy Lane - %d\n", - ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"), - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Scrath - %d\n", EngineList->Scratch); - IDS_HDT_CONSOLE (PCIE_MISC, " Init Status - 0x%08x\n", EngineList->InitStatus); - if (PcieLibIsPcieEngine (EngineList)) { - IDS_HDT_CONSOLE (PCIE_MISC, " PCIe port configuration:\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Port Training - %s\n", - (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled" - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane); - IDS_HDT_CONSOLE (PCIE_MISC, " End Core Lane - %d\n", EngineList->Type.Port.EndCoreLane); - IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Dev Number - %d\n",EngineList->Type.Port.PortData.DeviceNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Func Number - %d\n",EngineList->Type.Port.PortData.FunctionNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " PCI Address - %d:%d:%d\n", - EngineList->Type.Port.Address.Address.Bus, - EngineList->Type.Port.Address.Address.Device, - EngineList->Type.Port.Address.Address.Function - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - %d\n", EngineList->Type.Port.PortData.MiscControls); - IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); - IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", - (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : ( - (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown")))) - ); - ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug); - IDS_HDT_CONSOLE (PCIE_MISC, " ASPM - %s\n", - (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" : ( - (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown"))) - ); - ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm); - IDS_HDT_CONSOLE (PCIE_MISC, " Speed - %d\n", - EngineList->Type.Port.PortData.LinkSpeedCapability - ); - } else { - IDS_HDT_CONSOLE (PCIE_MISC, " DDI configuration:\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Connector - %s\n", - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : ( - (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown"))))))))))) - ); - ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType); - IDS_HDT_CONSOLE (PCIE_MISC, " Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1); - ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux); - IDS_HDT_CONSOLE (PCIE_MISC, " Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1); - ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump wrapper configuration - * - * - * @param[in] WrapperList Wrapper Configuration - */ -VOID -PcieConfigWrapperDebugDump ( - IN PCIe_WRAPPER_CONFIG *WrapperList - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n", - PcieFmDebugGetWrapperNameString (WrapperList) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " PowerOffUnusedLanes - %x\n PowerOffUnusedPlls - %x\n ClkGating - %x\n" - " LclkGating - %x\n TxclkGatingPllPowerDown - %x\n PllOffInL1 - %x\n", - WrapperList->Features.PowerOffUnusedLanes, - WrapperList->Features.PowerOffUnusedPlls, - WrapperList->Features.ClkGating, - WrapperList->Features.LclkGating, - WrapperList->Features.TxclkGatingPllPowerDown, - WrapperList->Features.PllOffInL1 - ); - IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config End----->\n", - PcieFmDebugGetWrapperNameString (WrapperList) - ); - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - PcieConfigEngineDebugDump (EngineList); - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump configuration to debug out - * - * - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieConfigDebugDump ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *SiliconList; - PCIe_WRAPPER_CONFIG *WrapperList; - PCIe_COMPLEX_CONFIG *ComplexList; - ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); - IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n", - (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" : - (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : ( - (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : ( - (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : ( - (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown"))) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n", - (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled" - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n", - Pcie->LinkL0Pooling - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n", - Pcie->LinkGpioResetAssertionTime - ); - IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n", - Pcie->LinkReceiverDetectionPooling - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n", - (Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : ( - (Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown") - ); - while (ComplexList != NULL) { - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId); - SiliconList = PcieConfigGetChildSilicon (ComplexList); - while (SiliconList != NULL) { - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n"); - IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags); - IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId); - IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n", - SiliconList->Address.Address.Bus, - SiliconList->Address.Address.Device, - SiliconList->Address.Address.Function - ); - WrapperList = PcieConfigGetChildWrapper (SiliconList); - while (WrapperList != NULL) { - PcieConfigWrapperDebugDump (WrapperList); - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n"); - SiliconList = PcieLibGetNextDescriptor (SiliconList); - } - IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n"); - ComplexList = PcieLibGetNextDescriptor (ComplexList); - } - IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n"); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Helper function to dump input configuration to debug out - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieUserConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor - ) -{ - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - PCIe_COMPLEX_DESCRIPTOR *CurrentComplexDescriptor; - UINTN ComplexIndex; - UINTN Index; - UINTN NumberOfEngines; - UINTN NumberOfComplexes; - - IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n"); - - NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor); - for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { - CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); - NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); - IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", - ComplexDescriptor->SocketId, - NumberOfEngines - ); - - for (Index = 0; Index < NumberOfEngines; Index++) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); - IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n", - (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : ( - (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : ( - (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid")) - ); - IDS_HDT_CONSOLE (PCIE_MISC, " Start Phy Lane - %d\n End Phy Lane - %d\n", - EngineDescriptor->EngineData.StartLane, - EngineDescriptor->EngineData.EndLane - ); - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n" , - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink - ); - } - if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " ConnectorType - %d\n AuxIndex - %d\n HdpIndex - %d\n" , - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType, - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex, - ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex - ); - } - } - } - IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n"); -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h deleted file mode 100644 index 682e336dda..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h +++ /dev/null @@ -1,202 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB function to create/locate PCIe configuration data area - * - * Contain code that create/locate and rebase configuration data area. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -#ifndef _PCIECONFIGLIB_H_ -#define _PCIECONFIGLIB_H_ - -typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -typedef AGESA_STATUS (*PCIe_RUN_ON_DESCRIPTOR_CALLBACK) ( - IN PCIe_DESCRIPTOR_HEADER *Descriptor, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -UINT8 -PcieConfigGetPcieEngineMasterLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT8 -PcieConfigGetNumberOfCoreLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -VOID -PcieConfigDisableAllEngines ( - IN UINTN EngineTypeMask, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PcieConfigDisableEngine ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT32 -PcieConfigGetEnginePhyLaneBitMap ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT8 -PcieConfigGetNumberOfPhyLane ( - IN PCIe_ENGINE_CONFIG *Engine - ); - -UINT64 -PcieConfigGetConfigurationSignature ( - IN PCIe_WRAPPER_CONFIG *Wrapper, - IN UINT8 CoreId - ); - -BOOLEAN -PcieConfigCheckPortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 PortStatus - ); - -UINT32 -PcieConfigUpdatePortStatus ( - IN PCIe_ENGINE_CONFIG *Engine, - IN UINT32 SetStatus, - IN UINT32 ResetStatus - ); - -VOID -PcieConfigRunProcForAllEngines ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieConfigRunProcForAllWrappers ( - IN UINT32 DescriptorFlags, - IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieConfigRunProcForAllDescriptors ( - IN UINT32 InDescriptorFlags, - IN UINT32 OutDescriptorFlags, - IN UINT32 TerminationFlags, - IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetParent ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetChild ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -PCIe_DESCRIPTOR_HEADER * -PcieConfigGetPeer ( - IN UINT32 Type, - IN PCIe_DESCRIPTOR_HEADER *Descriptor - ); - -VOID -PcieConfigDebugDump ( - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieConfigWrapperDebugDump ( - IN PCIe_WRAPPER_CONFIG *WrapperList - ); - -VOID -PcieConfigEngineDebugDump ( - IN PCIe_ENGINE_CONFIG *EngineList - ); - -VOID -PcieUserConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor - ); - -#define PcieConfigGetParentWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetParent (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) -#define PcieConfigGetParentSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &((Descriptor)->Header))) -#define PcieConfigGetParentComplex(Descriptor) ((PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &((Descriptor)->Header))) -#define PcieConfigGetPlatform(Descriptor) ((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header))) -#define PcieConfigGetChildWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) -#define PcieConfigGetChildEngine(Descriptor) ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header))) -#define PcieConfigGetChildSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header))) -#define PcieConfigGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) -#define PcieConfigIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0)) -#define PcieConfigIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0)) -#define PcieConfigIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0)) -#define PcieConfigIsSbPcieEngine(Engine) ((BOOLEAN) (Engine->Type.Port.PortData.MiscControls.SbLink)) -#define PcieConfigIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0)) -#define PcieConfigIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) -#define PcieConfigIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : (1==0)) -#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags -#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags)) -#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) -#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer)) - -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c deleted file mode 100644 index 5398ca1041..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +++ /dev/null @@ -1,256 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to parse PCIe input configuration data - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "PcieConfigLib.h" -#include "PcieInputParser.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -UINTN -PcieInputParserGetLengthOfDdiEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of complexes in platform topology configuration - * - * - * - * @param[in] ComplexList First complex configuration in complex configuration array - * @retval Number of Complexes - * - */ -UINTN -PcieInputParserGetNumberOfComplexes ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList - ) -{ - UINTN Result; - Result = 0; - if (ComplexList != NULL) { - while (ComplexList != NULL) { - Result++; - ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of PCIe engines in given complex - * - * - * - * @param[in] Complex Complex configuration - * @retval Number of Engines - */ -UINTN -PcieInputParserGetLengthOfPcieEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - CONST PCIe_PORT_DESCRIPTOR *PciePortList; - Result = 0; - if (Complex != NULL) { - PciePortList = Complex->PciePortList; - while (PciePortList != NULL) { - Result++; - PciePortList = PcieInputParsetGetNextDescriptor (PciePortList); - } - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of DDI engines in given complex - * - * - * - * @param[in] Complex Complex configuration - * @retval Number of Engines - */ -UINTN -PcieInputParserGetLengthOfDdiEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; - Result = 0; - if (Complex != NULL) { - DdiLinkList = Complex->DdiLinkList; - while (DdiLinkList != NULL) { - Result++; - DdiLinkList = PcieInputParsetGetNextDescriptor (DdiLinkList); - } - } - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get number of engines in given complex - * - * - * - * @param[in] Complex Complex configuration header - * @retval Number of Engines - */ -UINTN -PcieInputParserGetNumberOfEngines ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ) -{ - UINTN Result; - - Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) + - PcieInputParserGetLengthOfPcieEnginesList (Complex); - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Complex descriptor by index from given Platform configuration - * - * - * - * @param[in] ComplexList Platform topology configuration - * @param[in] Index Complex descriptor Index - * @retval Pointer to Complex Descriptor - */ -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINTN Index - ) -{ - ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList))); - return &ComplexList[Index]; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Complex descriptor by index from given Platform configuration - * - * - * - * @param[in] ComplexList Platform topology configuration - * @param[in] Index Complex descriptor Index - * @retval Pointer to Complex Descriptor - */ -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptorOfSocket ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINT32 SocketId - ) -{ - PCIe_COMPLEX_DESCRIPTOR *Result; - Result = NULL; - while (ComplexList != NULL) { - if (ComplexList->SocketId == SocketId ) { - Result = ComplexList; - break; - } - ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); - } - return Result; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Get Engine descriptor from given complex by index - * - * - * - * @param[in] Complex Complex descriptor - * @param[in] Index Engine descriptor index - * @retval Pointer to Engine Descriptor - */ -PCIe_ENGINE_DESCRIPTOR* -PcieInputParserGetEngineDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex, - IN UINTN Index - ) -{ - UINTN PcieListlength; - ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex))); - PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex); - if (Index < PcieListlength) { - return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]); - } else { - return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]); - } -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h deleted file mode 100644 index ed2e33ac69..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to parse PCIe input configuration data - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEINPUTPARSER_H_ -#define _PCIEINPUTPARSER_H_ - - -UINTN -PcieInputParserGetNumberOfComplexes ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *ComplexList - ); - -UINTN -PcieInputParserGetNumberOfEngines ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); - - -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINTN Index - ); - -PCIe_ENGINE_DESCRIPTOR* -PcieInputParserGetEngineDescriptor ( - IN PCIe_COMPLEX_DESCRIPTOR *Complex, - IN UINTN Index - ); - -PCIe_COMPLEX_DESCRIPTOR* -PcieInputParserGetComplexDescriptorOfSocket ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, - IN UINT32 SocketId - ); - -UINTN -PcieInputParserGetLengthOfPcieEnginesList ( - IN CONST PCIe_COMPLEX_DESCRIPTOR *Complex - ); -#endif - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c deleted file mode 100644 index 1c103f7ce1..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +++ /dev/null @@ -1,658 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to map user define topology to processor configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 49532 $ @e \$Date: 2011-03-25 02:54:43 +0800 (Fri, 25 Mar 2011) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "amdlib.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "GeneralServices.h" -#include "PcieInputParser.h" -#include "PcieMapTopology.h" -#include "GnbPcieConfig.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -AGESA_STATUS -STATIC -PcieMapPortsPciAddresses ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -AGESA_STATUS -PcieMapTopologyOnWrapper ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -VOID -PcieMapInitializeEngineData ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -PcieCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -VOID -PcieComplexConfigConfigDump ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -BOOLEAN -PcieIsDescriptorLinkWidthValid ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor - ); - -BOOLEAN -PcieCheckLanesMatch ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ); - -AGESA_STATUS -PcieEnginesToWrapper ( - IN PCIE_ENGINE_TYPE EngineType, - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -BOOLEAN -PcieCheckDescriptorMapsToWrapper ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ); - -VOID -PcieAllocateEngine ( - IN UINT8 DescriptorIndex, - IN PCIe_ENGINE_CONFIG *Engine - ); -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Complex Pointer to complex descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ - -AGESA_STATUS -PcieMapTopologyOnComplex ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_COMPLEX_CONFIG *Complex, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_SILICON_CONFIG *Silicon; - PCIe_WRAPPER_CONFIG *Wrapper; - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - - AgesaStatus = AGESA_SUCCESS; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n"); - Silicon = PcieConfigGetChildSilicon (Complex); - while (Silicon != NULL) { - Wrapper = PcieConfigGetChildWrapper (Silicon); - while (Wrapper != NULL) { - Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n", - PcieFmDebugGetWrapperNameString (Wrapper) - ); - ASSERT (FALSE); - } - Wrapper = PcieLibGetNextDescriptor (Wrapper); - } - Status = PcieMapPortsPciAddresses (Silicon, Pcie); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - Silicon = PcieLibGetNextDescriptor (Silicon); - } - IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus); - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * - * - * @param[in] EngineType Engine type - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in] Wrapper Pointer to wrapper config descriptor - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ -AGESA_STATUS -PcieEnginesToWrapper ( - IN PCIE_ENGINE_TYPE EngineType, - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - AGESA_STATUS Status; - PCIe_ENGINE_CONFIG *EngineList; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - UINT8 ConfigurationId; - UINT8 Allocations; - UINTN Index; - UINTN NumberOfDescriptors; - - ConfigurationId = 0; - Allocations = 0; - IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n"); - NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor); - do { - Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++); - - if (Status == AGESA_SUCCESS) { - Allocations = 0; - for (Index = 0; Index < NumberOfDescriptors; Index++) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); - if (EngineDescriptor->EngineData.EngineType == EngineType) { - // Step 1, belongs to wrapper check. - if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) { - ++Allocations; - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (!PcieLibIsEngineAllocated (EngineList)) { - // Step 2.user descriptor less or equal to link width of engine - if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) { - // Step 3, Check if link width is correct.x1, x2, x4, x8, x16. - if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) { - PcieConfigDisableEngine (EngineList); - return AGESA_ERROR; - } - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - // Step 4, Family specifc, port device number match engine device - if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { - //Step 5, Family specifc, lanes can be muxed. - if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { - PcieAllocateEngine ((UINT8) Index, EngineList); - --Allocations; - break; - } - } - } else { - PcieAllocateEngine ((UINT8) Index, EngineList); - --Allocations; - break; - } - } - }//end if PcieLibIsEngineAllocated - EngineList = PcieLibGetNextDescriptor (EngineList); - } - }//end if PcieCheckDescriptorMapsToWrapper - }// end if EngineType - }//end for - } - } while (Status == AGESA_SUCCESS && Allocations != 0); - IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * - * - * @param[in] EngineDescriptor Pointer to used define engine descriptor - * @param[in] Wrapper Pointer to PCIe_WRAPPER_CONFIG - * @retval TRUE Belongs to wrapper - * @retval FALSE Not belongs to wrapper - */ -BOOLEAN -PcieCheckDescriptorMapsToWrapper ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_WRAPPER_CONFIG *Wrapper - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - Result = TRUE; - - if (!(DescriptorLoLane >= Wrapper->StartPhyLane && DescriptorHiLane <= Wrapper->EndPhyLane)) { - // Lanes of descriptor does not belongs to wrapper - Result = FALSE; - } - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Set Engine to be allocated. - * - * - * @param[in] DescriptorIndex UINT8 index - * @param[in] Engine Pointer to engine config - */ -VOID -PcieAllocateEngine ( - IN UINT8 DescriptorIndex, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - PcieConfigSetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); - Engine->Scratch = DescriptorIndex; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Configure engine list to support lane allocation according to configuration ID. - * - * PCIE port - * - * - * 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) - * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 - * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG) - * 5 Check if lane can be muxed - * - * - * DDI Link - * - * 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) - * 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) - * - * - * - * @param[in] ComplexDescriptor Pointer to used define complex descriptor - * @param[in,out] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_SUCCESS Topology successfully mapped - * @retval AGESA_ERROR Topology can not be mapped - */ -AGESA_STATUS -PcieMapTopologyOnWrapper ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS AgesaStatus; - AGESA_STATUS Status; - PCIe_ENGINE_CONFIG *EngineList; - UINT32 WrapperPhyLaneBitMap; - - AgesaStatus = AGESA_SUCCESS; - if (PcieLibIsPcieWrapper (Wrapper)) { - Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - // If we can not map topology on wrapper we can not enable any engines. - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION, - Wrapper->WrapId, - Wrapper->StartPhyLane, - Wrapper->EndPhyLane, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableAllEngines (PciePortEngine, Wrapper); - } - } - if (PcieLibIsDdiWrapper (Wrapper)) { - Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_ERROR) { - // If we can not map topology on wrapper we can not enable any engines. - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION, - Wrapper->WrapId, - Wrapper->StartPhyLane, - Wrapper->EndPhyLane, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper); - } - } - // Copy engine data - PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie); - - EngineList = PcieConfigGetChildEngine (Wrapper); - // Verify if we oversubscribe lanes and PHY link width - WrapperPhyLaneBitMap = 0; - while (EngineList != NULL) { - UINT32 EnginePhyLaneBitMap; - if (PcieLibIsEngineAllocated (EngineList)) { - EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList); - if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) { - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n", - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane - ); - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_LANES_CONFIGURATION, - EngineList->EngineData.StartLane, - EngineList->EngineData.EndLane, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - PcieConfigDisableEngine (EngineList); - Status = AGESA_ERROR; - AGESA_STATUS_UPDATE (Status, AgesaStatus); - } else { - WrapperPhyLaneBitMap |= EnginePhyLaneBitMap; - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - return AgesaStatus; -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Initialize engine data - * - * - * - * @param[in] ComplexDescriptor Pointer to user defined complex descriptor - * @param[in,out] Wrapper Pointer to wrapper config descriptor - * @param[in] Pcie Pointer to global PCIe configuration - */ -VOID -PcieMapInitializeEngineData ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN OUT PCIe_WRAPPER_CONFIG *Wrapper, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIe_ENGINE_CONFIG *EngineList; - PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; - - EngineList = PcieConfigGetChildEngine (Wrapper); - while (EngineList != NULL) { - if (PcieLibIsEngineAllocated (EngineList)) { - if (EngineList->Scratch != 0xFF) { - EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch); - LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie)); - if (PcieLibIsDdiEngine (EngineList)) { - LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie)); - EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch; - } else if (PcieLibIsPcieEngine (EngineList)) { - LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie)); - } - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate PCI addresses for all PCIe engines on silicon - * - * - * - * @param[in] PortDescriptor Pointer to user defined engine descriptor - * @param[in] Engine Pointer engine configuration - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieCheckPortPciDeviceMapping ( - IN PCIe_PORT_DESCRIPTOR *PortDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - BOOLEAN Result; - - if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber && - PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) || - (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) { - Result = TRUE; - } else { - Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); - } - - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Allocate PCI addresses for all PCIe engines on silicon - * - * - * - * @param[in] Silicon Pointer to silicon configurration - * @param[in] Pcie Pointer PCIe configuration - * @retval AGESA_ERROR Fail to allocate PCI device address - * @retval AGESA_SUCCESS Successfully allocate PCI address for all PCIe ports - */ - -AGESA_STATUS -STATIC -PcieMapPortsPciAddresses ( - IN PCIe_SILICON_CONFIG *Silicon, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - AGESA_STATUS AgesaStatus; - PCIe_WRAPPER_CONFIG *WrapperList; - PCIe_ENGINE_CONFIG *EngineList; - AgesaStatus = AGESA_SUCCESS; - WrapperList = PcieConfigGetChildWrapper (Silicon); - while (WrapperList != NULL) { - EngineList = PcieConfigGetChildEngine (WrapperList); - while (EngineList != NULL) { - if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { - Status = PcieFmMapPortPciAddress (EngineList); - AGESA_STATUS_UPDATE (Status, AgesaStatus); - if (Status == AGESA_SUCCESS) { - EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO ( - 0, - Silicon->Address.Address.Bus, - EngineList->Type.Port.PortData.DeviceNumber, - EngineList->Type.Port.PortData.FunctionNumber, - 0 - ); - } else { - EngineList->Type.Port.PortData.PortPresent = OFF; - IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n" - ); - //Report error - PutEventLog ( - AGESA_ERROR, - GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION, - EngineList->Type.Port.PortData.DeviceNumber, - 0, - 0, - 0, - GnbLibGetHeader (Pcie) - ); - } - } - EngineList = PcieLibGetNextDescriptor (EngineList); - } - WrapperList = PcieLibGetNextDescriptor (WrapperList); - } - return AgesaStatus; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * If link width from user descriptor less or equal to link width of engine - * - * - * @param[in] EngineDescriptor Pointer to used define engine descriptor - * @param[in] Engine Pointer to engine config - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieCheckLanesMatch ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, - IN PCIe_ENGINE_CONFIG *Engine - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - Result = FALSE; - - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - // - // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) - // - if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) { - Result = TRUE; - } - } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - // - //For Ddi, check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) - // - if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) { - Result = TRUE; - } - } - - return Result; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 - * - * - * @param[in] EngineDescriptor A pointer of PCIe_ENGINE_DESCRIPTOR - * @retval TRUE Descriptor can be mapped to engine - * @retval FALSE Descriptor can NOT be mapped to engine - */ - -BOOLEAN -PcieIsDescriptorLinkWidthValid ( - IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor - ) -{ - BOOLEAN Result; - UINT16 DescriptorHiLane; - UINT16 DescriptorLoLane; - UINT16 DescriptorNumberOfLanes; - - Result = FALSE; - DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); - DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; - - if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 || - DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) { - Result = TRUE; - } - } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { - if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 7) { - Result = TRUE; - } - } - - GNB_DEBUG_CODE ( - if (!Result) { - IDS_HDT_CONSOLE (PCIE_MISC, " Invalid Link width [Engine Lanes %d..%d]\n", - DescriptorLoLane, - DescriptorHiLane - ); - } - ); - - return Result; -} - diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h deleted file mode 100644 index d68429d55d..0000000000 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h +++ /dev/null @@ -1,57 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Procedure to map user define topology to processor configuration - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $ - * - */ -/* -***************************************************************************** -* -* Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -#ifndef _PCIEMAPTOPOLOGY_H_ -#define _PCIEMAPTOPOLOGY_H_ - -AGESA_STATUS -PcieMapTopologyOnComplex ( - IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, - IN PCIe_COMPLEX_CONFIG *Complex, - IN PCIe_PLATFORM_CONFIG *Pcie - ); - -#endif - - |