Add AMD Family 12 cpu Agesa code

This is the addition of the AMD Family 12 cpu code.

Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c
Signed-off-by: Frank Vibrans<frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/40
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

20 files changed, 4188 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h
new file mode 100755
index 0000000000..9c6093ec31
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h
@@ -0,0 +1,66 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific service routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXFAMILYSERVICES_H_
+#define _GFXFAMILYSERVICES_H_
+
+VOID
+GfxFmIntegratedInfoTableInit (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxFmGmcAddressSwizzel (
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxFmGmcAllowPstateHigh (
+  IN      GFX_PLATFORM_CONFIG               *Gfx
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
new file mode 100755
index 0000000000..6ece971bf0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
@@ -0,0 +1,671 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics Controller family specific service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 51088 $   @e \$Date: 2011-04-19 07:40:52 +0800 (Tue, 19 Apr 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "GeneralServices.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GfxIntegratedInfoTableInit.h"
+#include  "GfxRegisterAcc.h"
+#include  "GfxLib.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbCommonLib.h"
+#include  "NbSmuLib.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxFamilyServices.h"
+#include  "GnbRegistersLN.h"
+#include  "F12NbPowerGate.h"
+#include  "F12PackageType.h"
+#include  "cpuFamilyTranslation.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+UINT8 NumberOfChannels = 2;
+
+UINT8  DdiLaneConfigArray [][4] = {
+  {31, 24, 1, 0},
+  {24, 31, 0, 1},
+  {24, 27, 0, 0},
+  {27, 24, 0, 0},
+  {28, 31, 1, 1},
+  {31, 28, 1, 1},
+  {8 , 15, 2, 3},
+  {8,  11, 2, 2},
+  {11, 8 , 2, 2},
+  {15, 8 , 3, 2},
+  {12, 15, 3, 3},
+  {15, 12, 3, 3},
+  {16, 23, 4, 5},
+  {16, 19, 4, 4},
+  {19, 16, 4, 4},
+  {23, 16, 5, 4},
+  {20, 23, 5, 5},
+  {23, 20, 5, 5},
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize display path for given engine
+ *
+ *
+ *
+ * @param[in]   Engine            Engine configuration info
+ * @param[out]  DisplayPathList   Display path list
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ */
+
+AGESA_STATUS
+GfxFmMapEngineToDisplayPath (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  AGESA_STATUS      Status;
+  UINT8             PrimaryDisplayPathId;
+  UINT8             SecondaryDisplayPathId;
+  UINTN             DisplayPathIndex;
+  PrimaryDisplayPathId = 0xff;
+  SecondaryDisplayPathId = 0xff;
+  for (DisplayPathIndex = 0; DisplayPathIndex <  (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) {
+    if (DdiLaneConfigArray[DisplayPathIndex][0] == Engine->EngineData.StartLane &&
+        DdiLaneConfigArray[DisplayPathIndex][1] == Engine->EngineData.EndLane) {
+      PrimaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][2];
+      SecondaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][3];
+      break;
+    }
+  }
+  if (PrimaryDisplayPathId != 0xff) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId);
+    Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE;
+    GfxIntegratedCopyDisplayInfo (
+      Engine,
+      &DisplayPathList[PrimaryDisplayPathId],
+      (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL,
+      Gfx
+      );
+    Status = AGESA_SUCCESS;
+  } else {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Error!!! Map DDI lanes %d - %d to display path failed\n",
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane
+      );
+    PutEventLog (
+      AGESA_ERROR,
+      GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION,
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane,
+      0,
+      0,
+      GnbLibGetHeader (Gfx)
+      );
+    Status = AGESA_ERROR;
+  }
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Family specific integrated info table init
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxFmIntegratedInfoTableInit (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380;
+  IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 3400;
+  IntegratedInfoTable->ulGMCRestoreResetTime = F12NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx));
+  if (((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) && ((LibAmdGetPackageType (GnbLibGetHeader (Gfx)) & PACKAGE_TYPE_FM1) != 0)) {
+    GnbLibPciRMW (
+      MAKE_SBDFO (0, 0, 0x18, 6, D18F6x78_ADDRESS),
+      AccessS3SaveWidth32,
+      0xffffffff,
+      1 << D18F6x78_DispArbCtrl_OFFSET,
+      GnbLibGetHeader (Gfx)
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Family specific address swizzle settings.
+ *
+ *
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxFmGmcAddressSwizzel (
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  GMMx2864_STRUCT GMMx2864;
+  GMMx2868_STRUCT GMMx2868;
+  UCHAR           EffectiveChannels;
+  GMMx2864.Value = GmmRegisterRead (GMMx2864_ADDRESS, Gfx);
+  if (GMMx2864.Value == 0) {
+    // Check if two memory channels
+    EffectiveChannels = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
+    if (EffectiveChannels == 2) {
+      GMMx2864.Value = 0x32009817;  // Value for two channels
+      GMMx2868.Value = 0x00000004;
+      GmmRegisterWrite (GMMx2868_ADDRESS, GMMx2868.Value, TRUE, Gfx);
+    } else {
+      GMMx2864.Value = 0x32100876;  // Value for single channel
+    }
+    GmmRegisterWrite (
+      GMMx2864_ADDRESS,
+      GMMx2864.Value,
+      TRUE,
+      Gfx
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+GfxFmGmcAllowPstateHigh (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate COF for DFS out of Main PLL
+ *
+ *
+ *
+ * @param[in] Did         Did
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                COF in 10khz
+ */
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32  MainPllFreq10kHz;
+  MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100;
+  return GfxLibCalculateClk (Did, MainPllFreq10kHz);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set idle voltage mode for GFX
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+GfxFmSetIdleVoltageMode (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  FCRxFF30_0191_STRUCT   FCRxFF30_0191;
+  NbSmuSrbmRegisterRead (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, GnbLibGetHeader (Gfx));
+  FCRxFF30_0191.Field.GfxIdleVoltChgMode = (Gfx->GfxFusedOff || Gfx->UmaInfo.UmaMode != UMA_NONE) ? 0x0 : 0x1;
+  NbSmuSrbmRegisterWrite (FCRxFF30_0191_ADDRESS, &FCRxFF30_0191.Value, TRUE, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------
+ *           GMC Disable Clock Gating
+ *----------------------------------------------------------------------------------------
+ */
+
+
+GMM_REG_ENTRY  GmcDisableClockGating[] = {
+  { GMMx20C0_ADDRESS, 0x00000C80 },
+  { GMMx2478_ADDRESS, 0x00000400 },
+  { GMMx20B8_ADDRESS, 0x00000400 },
+  { GMMx20BC_ADDRESS, 0x00000400 },
+  { GMMx2650_ADDRESS, 0x00000400 },
+  { GMMx2654_ADDRESS, 0x00000400 },
+  { GMMx2658_ADDRESS, 0x00000400 },
+  { GMMx15C0_ADDRESS, 0x00081401 }
+};
+
+TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = {
+  sizeof (GmcDisableClockGating) / sizeof (GMM_REG_ENTRY),
+  GmcDisableClockGating
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *           GMC Enable Clock Gating
+ *----------------------------------------------------------------------------------------
+ */
+GMM_REG_ENTRY  GmcEnableClockGating[] = {
+  { GMMx20C0_ADDRESS, 0x00040C80 },
+  { GMMx2478_ADDRESS, 0x00040400 },
+  { GMMx20B8_ADDRESS, 0x00040400 },
+  { GMMx20BC_ADDRESS, 0x00040400 },
+  { GMMx2650_ADDRESS, 0x00040400 },
+  { GMMx2654_ADDRESS, 0x00040400 },
+  { GMMx2658_ADDRESS, 0x00040400 },
+  { GMMx15C0_ADDRESS, 0x000C1401 }
+};
+
+
+TABLE_INDIRECT_PTR GmcEnableClockGatingPtr = {
+  sizeof (GmcEnableClockGating) / sizeof (GMM_REG_ENTRY),
+  GmcEnableClockGating
+};
+
+/*----------------------------------------------------------------------------------------
+ *           GMC Performance Tuning
+ *----------------------------------------------------------------------------------------
+ */
+GMM_REG_ENTRY  GmcPerformanceTuningTable [] = {
+  { GMMx27CC_ADDRESS, 0x00032005 },
+  { GMMx27DC_ADDRESS, 0x00734847 },
+  { GMMx27D0_ADDRESS, 0x00012008 },
+  { GMMx27E0_ADDRESS, 0x00003D3C },
+  { GMMx2784_ADDRESS, 0x00000007 },
+  { GMMx21C8_ADDRESS, 0x0000A1F1 },
+  { GMMx217C_ADDRESS, 0x0000A1F1 },
+  { GMMx2188_ADDRESS, 0x000221b1 },
+  { GMMx2814_ADDRESS, 0x00000200 },
+  { GMMx201C_ADDRESS, 0x03330003 },
+  { GMMx2020_ADDRESS, 0x70760007 },
+  { GMMx2018_ADDRESS, 0x00000050 },
+  { GMMx2014_ADDRESS, 0x00005500 },
+  { GMMx2620_ADDRESS, 0x44111222 },
+  { GMMx2628_ADDRESS, 0x44111666 },
+  { GMMx2630_ADDRESS, 0x00000044 },
+  { GMMx2624_ADDRESS, 0x11333111 },
+  { GMMx262C_ADDRESS, 0x21444222 },
+  { GMMx2634_ADDRESS, 0x00000043 },
+  { GMMx279C_ADDRESS, 0xfcfcfdfc },
+  { GMMx27A0_ADDRESS, 0xfcfcfdfc }
+};
+
+TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = {
+  sizeof (GmcPerformanceTuningTable) / sizeof (GMM_REG_ENTRY),
+  GmcPerformanceTuningTable
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *           GMC Misc init table
+ *----------------------------------------------------------------------------------------
+ */
+GMM_REG_ENTRY  GmcMiscInitTable [] = {
+  { GMMx25C8_ADDRESS, 0x007F605F },
+  { GMMx25CC_ADDRESS, 0x00007F7E },
+  { GMMx28EC_ADDRESS, 0x00187000 },
+  { GMMx202C_ADDRESS, 0x0003FFFF }
+};
+
+TABLE_INDIRECT_PTR GmcMiscInitTablePtr = {
+  sizeof (GmcMiscInitTable) / sizeof (GMM_REG_ENTRY),
+  GmcMiscInitTable
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *           GMC Remove blackout
+ *----------------------------------------------------------------------------------------
+ */
+GMM_REG_ENTRY  GmcRemoveBlackoutTable [] = {
+  { GMMx25C0_ADDRESS, 0x00000000 },
+  { GMMx20EC_ADDRESS, 0x000001FC },
+  { GMMx20D4_ADDRESS, 0x00000016 }
+};
+
+TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = {
+  sizeof (GmcRemoveBlackoutTable) / sizeof (GMM_REG_ENTRY),
+  GmcRemoveBlackoutTable
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           GMC Register Engine Init Table
+ *----------------------------------------------------------------------------------------
+ */
+
+GMM_REG_ENTRY GmcRegisterEngineInitTable [] = {
+  { GMMx2B8C_ADDRESS, 0x00000000 },
+  { GMMx2B90_ADDRESS, 0x001e0a07 },
+  { GMMx2B8C_ADDRESS, 0x00000020 },
+  { GMMx2B90_ADDRESS, 0x00050500 },
+  { GMMx2B8C_ADDRESS, 0x00000027 },
+  { GMMx2B90_ADDRESS, 0x0001050c },
+  { GMMx2B8C_ADDRESS, 0x0000002a },
+  { GMMx2B90_ADDRESS, 0x0001051c },
+  { GMMx2B8C_ADDRESS, 0x0000002d },
+  { GMMx2B90_ADDRESS, 0x00030534 },
+  { GMMx2B8C_ADDRESS, 0x00000032 },
+  { GMMx2B90_ADDRESS, 0x0001053e },
+  { GMMx2B8C_ADDRESS, 0x00000035 },
+  { GMMx2B90_ADDRESS, 0x00010546 },
+  { GMMx2B8C_ADDRESS, 0x00000038 },
+  { GMMx2B90_ADDRESS, 0x0002054e },
+  { GMMx2B8C_ADDRESS, 0x0000003c },
+  { GMMx2B90_ADDRESS, 0x00010557 },
+  { GMMx2B8C_ADDRESS, 0x0000003f },
+  { GMMx2B90_ADDRESS, 0x0001055f },
+  { GMMx2B8C_ADDRESS, 0x00000042 },
+  { GMMx2B90_ADDRESS, 0x00010567 },
+  { GMMx2B8C_ADDRESS, 0x00000045 },
+  { GMMx2B90_ADDRESS, 0x0001056f },
+  { GMMx2B8C_ADDRESS, 0x00000048 },
+  { GMMx2B90_ADDRESS, 0x00050572 },
+  { GMMx2B8C_ADDRESS, 0x0000004f },
+  { GMMx2B90_ADDRESS, 0x00000800 },
+  { GMMx2B8C_ADDRESS, 0x00000051 },
+  { GMMx2B90_ADDRESS, 0x00260801 },
+  { GMMx2B8C_ADDRESS, 0x00000079 },
+  { GMMx2B90_ADDRESS, 0x004b082d },
+  { GMMx2B8C_ADDRESS, 0x000000c6 },
+  { GMMx2B90_ADDRESS, 0x0013088d },
+  { GMMx2B8C_ADDRESS, 0x000000db },
+  { GMMx2B90_ADDRESS, 0x100008a1 },
+  { GMMx2B90_ADDRESS, 0x00000040 },
+  { GMMx2B90_ADDRESS, 0x00000040 },
+  { GMMx2B8C_ADDRESS, 0x000000df },
+  { GMMx2B90_ADDRESS, 0x000008a2 },
+  { GMMx2B8C_ADDRESS, 0x000000e1 },
+  { GMMx2B90_ADDRESS, 0x005a08cd },
+  { GMMx2B8C_ADDRESS, 0x0000013d },
+  { GMMx2B90_ADDRESS, 0x0001094d },
+  { GMMx2B8C_ADDRESS, 0x00000140 },
+  { GMMx2B90_ADDRESS, 0x00000952 },
+  { GMMx2B8C_ADDRESS, 0x00000142 },
+  { GMMx2B90_ADDRESS, 0x00010954 },
+  { GMMx2B8C_ADDRESS, 0x00000145 },
+  { GMMx2B90_ADDRESS, 0x0009095a },
+  { GMMx2B8C_ADDRESS, 0x00000150 },
+  { GMMx2B90_ADDRESS, 0x0029096d },
+  { GMMx2B8C_ADDRESS, 0x0000017b },
+  { GMMx2B90_ADDRESS, 0x000e0997 },
+  { GMMx2B8C_ADDRESS, 0x0000018b },
+  { GMMx2B90_ADDRESS, 0x100009a6 },
+  { GMMx2B90_ADDRESS, 0x00000040 },
+  { GMMx2B90_ADDRESS, 0x00000040 },
+  { GMMx2B8C_ADDRESS, 0x0000018f },
+  { GMMx2B90_ADDRESS, 0x000009a7 },
+  { GMMx2B8C_ADDRESS, 0x00000191 },
+  { GMMx2B90_ADDRESS, 0x002e09d7 },
+  { GMMx2B8C_ADDRESS, 0x000001c1 },
+  { GMMx2B90_ADDRESS, 0x00170a26 },
+  { GMMx2B94_ADDRESS, 0x765d9000 },
+  { GMMx2B98_ADDRESS, 0x410af020 }
+};
+
+TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = {
+  sizeof (GmcRegisterEngineInitTable) / sizeof (GMM_REG_ENTRY),
+  GmcRegisterEngineInitTable
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *           GMC Address Translation Table
+ *----------------------------------------------------------------------------------------
+ */
+REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = {
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x040_ADDRESS),
+    GMMx281C_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x140_ADDRESS),
+    GMMx2820_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x044_ADDRESS),
+    GMMx2824_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x144_ADDRESS),
+    GMMx2828_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x048_ADDRESS),
+    GMMx282C_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x148_ADDRESS),
+    GMMx2830_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x04C_ADDRESS),
+    GMMx2834_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x14C_ADDRESS),
+    GMMx2838_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x060_ADDRESS),
+    GMMx283C_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x064_ADDRESS),
+    GMMx2840_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x160_ADDRESS),
+    GMMx2844_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x164_ADDRESS),
+    GMMx2848_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x080_ADDRESS),
+    GMMx284C_ADDRESS,
+    D18F2x080_Dimm0AddrMap_OFFSET,
+    D18F2x080_Dimm0AddrMap_WIDTH + D18F2x080_Dimm1AddrMap_WIDTH,
+    GMMx284C_Dimm0AddrMap_OFFSET,
+    GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS),
+    GMMx284C_ADDRESS,
+    D18F2x094_BankSwizzleMode_OFFSET,
+    D18F2x094_BankSwizzleMode_WIDTH,
+    GMMx284C_BankSwizzleMode_OFFSET,
+    GMMx284C_BankSwizzleMode_WIDTH
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x0A8_ADDRESS),
+    GMMx284C_ADDRESS,
+    D18F2x0A8_BankSwap_OFFSET,
+    D18F2x0A8_BankSwap_WIDTH,
+    GMMx284C_BankSwap_OFFSET,
+    GMMx284C_BankSwap_WIDTH
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x180_ADDRESS),
+    GMMx2850_ADDRESS,
+    D18F2x180_Dimm0AddrMap_OFFSET,
+    D18F2x180_Dimm0AddrMap_WIDTH + D18F2x180_Dimm1AddrMap_WIDTH,
+    GMMx2850_Dimm0AddrMap_OFFSET,
+    GMMx2850_Dimm0AddrMap_WIDTH + GMMx2850_Dimm1AddrMap_WIDTH
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x194_ADDRESS),
+    GMMx2850_ADDRESS,
+    D18F2x194_BankSwizzleMode_OFFSET,
+    D18F2x194_BankSwizzleMode_WIDTH,
+    GMMx2850_BankSwizzleMode_OFFSET,
+    GMMx2850_BankSwizzleMode_WIDTH
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x1A8_ADDRESS),
+    GMMx2850_ADDRESS,
+    D18F2x1A8_BankSwap_OFFSET,
+    D18F2x1A8_BankSwap_WIDTH,
+    GMMx2850_BankSwap_OFFSET,
+    GMMx2850_BankSwap_WIDTH
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS),
+    GMMx2854_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS),
+    GMMx2858_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 1, D18F1xF0_ADDRESS),
+    GMMx285C_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  },
+  {
+    MAKE_SBDFO (0, 0, 0x18, 2, D18F2x10C_ADDRESS),
+    GMMx2860_ADDRESS,
+    0,
+    31,
+    0,
+    31
+  }
+};
+
+
+TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = {
+  sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY),
+  CnbToGncRegisterCopyTable
+};
+
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c
new file mode 100755
index 0000000000..561d8571aa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c
@@ -0,0 +1,131 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 50010 $   @e \$Date: 2011-03-31 18:07:03 +0800 (Thu, 31 Mar 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GfxStrapsInit.h"
+#include  "OptionGnb.h"
+#include  "GfxConfigData.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG      UserOptions;
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable GMM Access
+ *
+ *
+ *
+ * @param[in,out]   Gfx            Pointer to GFX configuration
+ * @retval          AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxEnableGmmAccess (
+  IN OUT   GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32      Value;
+
+  if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+
+  // Check if base address for GMM allocated
+  GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx));
+  if (Gfx->GmmBase == 0) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+  // Check if base address for FB allocated
+  GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
+  if ((Value & 0xfffffff0) == 0) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+  //Push CPU MMIO pci config to S3 script
+  GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+  // Turn on memory decoding on APC to enable access to GMM register space
+  if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
+    GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
+    //Push APC pci config to S3 script
+    GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+    GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
+  }
+  // Turn on memory decoding on GFX to enable access to GMM register space
+  GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
+  //Push iGPU pci config to S3 script
+  GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+  GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h
new file mode 100755
index 0000000000..bb0ba62807
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXCONFIGDATA_H_
+#define _GFXCONFIGDATA_H_
+
+AGESA_STATUS
+GfxAllocateConfigData (
+  IN       AMD_CONFIG_PARAMS          *StdHeader,
+  IN OUT   GFX_PLATFORM_CONFIG        **Gfx,
+  IN       PLATFORM_CONFIGURATION     *PlatformConfig
+  );
+
+AGESA_STATUS
+GfxEnableGmmAccess (
+  IN OUT  GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+AGESA_STATUS
+GfxConfigEnvInterface (
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+/*
+  VOID
+GfxGetUmaInfo (
+     OUT   UMA_INFO                   *UmaInfo,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+*/
+#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
new file mode 100755
index 0000000000..5c5ab45e24
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c
@@ -0,0 +1,797 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  GMC init services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 50763 $   @e \$Date: 2011-04-14 06:25:56 +0800 (Thu, 14 Apr 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+//#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbPcie.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GfxLib.h"
+#include  "GfxFamilyServices.h"
+#include  "GfxRegisterAcc.h"
+#include  "OptionGnb.h"
+#include  "GnbRegistersLN.h"
+#include  "GfxGmcInit.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXGMCINIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/// DCT channel information
+typedef struct {
+  D18F2x094_STRUCT      D18F2x094;          ///< Register 0x94
+  D18F2x084_STRUCT      D18F2x084;          ///< Register 0x84
+  D18F2x08C_STRUCT      D18F2x08C;          ///< Register 0x8C
+  D18F2x0F4_x40_STRUCT  D18F2x0F4_x40;      ///< Register 0x40
+  D18F2x0F4_x41_STRUCT  D18F2x0F4_x41;      ///< Register 0x41
+} DCT_CHANNEL_INFO;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GfxGmcSetMemoryAddressTranslation (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcDisableClockGating (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcInitializeRegisterEngine (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcDctMemoryChannelInfo (
+  IN       UINT8                 Channel,
+     OUT   DCT_CHANNEL_INFO      *DctChannelInfo,
+  IN       GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcInitializeSequencerModel (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcInitializeFbLocation (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcSecureGarlicAccess (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcPerformanceTuning (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcMiscInit (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcLockCriticalRegisters (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcRemoveBlackout (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcEnableClockGating (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcUmaSteering (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcInitializeC6Aperture (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxGmcInitializePowerGating (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//Family 12 or Family 14 specific tables
+
+extern TABLE_INDIRECT_PTR GmcDisableClockGatingPtr;
+extern TABLE_INDIRECT_PTR GmcEnableClockGatingPtr;
+extern TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr;
+extern TABLE_INDIRECT_PTR GmcMiscInitTablePtr;
+extern TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr;
+extern TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr;
+extern TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr;
+
+extern UINT8               NumberOfChannels;
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GMC memory address translation
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+VOID
+GfxGmcSetMemoryAddressTranslation (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINTN Index;
+  REGISTER_COPY_ENTRY *CnbToGncRegisterCopyTable;
+  CnbToGncRegisterCopyTable = CnbToGncRegisterCopyTablePtr.TablePtr;
+  for (Index = 0; Index < CnbToGncRegisterCopyTablePtr.TableLength; Index++) {
+    UINT32  Value;
+    GnbLibPciRead (
+      CnbToGncRegisterCopyTable[Index].CpuReg,
+      AccessWidth32,
+      &Value,
+      GnbLibGetHeader (Gfx)
+      );
+    Value = (Value >> CnbToGncRegisterCopyTable[Index].CpuOffset) & ((1 <<  CnbToGncRegisterCopyTable[Index].CpuWidth) - 1);
+    GmmRegisterWriteField (
+      CnbToGncRegisterCopyTable[Index].GmmReg,
+      CnbToGncRegisterCopyTable[Index].GmmOffset,
+      CnbToGncRegisterCopyTable[Index].GmmWidth,
+      Value,
+      TRUE,
+      Gfx
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable CLock Gating
+ *
+ *
+ *
+ * @param[in] Gfx         Graphics configuration
+ */
+
+VOID
+GfxGmcDisableClockGating (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GmmRegisterTableWrite (
+    GmcDisableClockGatingPtr.TablePtr,
+    GmcDisableClockGatingPtr.TableLength,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Register Engine
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcInitializeRegisterEngine (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+
+  GmmRegisterTableWrite (
+    GmcRegisterEngineInitTablePtr.TablePtr,
+    GmcRegisterEngineInitTablePtr.TableLength,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get DCT channel info
+ *
+ *
+ * @param[in]  Channel         DCT channel number
+ * @param[out] DctChannelInfo  Various DCT channel info
+ * @param[in]  Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcDctMemoryChannelInfo (
+  IN       UINT8                 Channel,
+     OUT   DCT_CHANNEL_INFO      *DctChannelInfo,
+  IN       GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GnbLibCpuPciIndirectRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS),
+    D18F2x0F4_x40_ADDRESS,
+    &DctChannelInfo->D18F2x0F4_x40.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibCpuPciIndirectRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS),
+    D18F2x0F4_x41_ADDRESS,
+    &DctChannelInfo->D18F2x0F4_x41.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS),
+    AccessWidth32,
+    &DctChannelInfo->D18F2x084.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS),
+    AccessWidth32,
+    &DctChannelInfo->D18F2x094.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS),
+    AccessWidth32,
+    &DctChannelInfo->D18F2x08C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Sequencer Model
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcInitializeSequencerModel (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx277C_STRUCT       GMMx277C;
+  GMMx2780_STRUCT       GMMx2780;
+  DCT_CHANNEL_INFO      DctChannel[2];
+  UINT8                 ActiveChannel;
+
+  GfxGmcDctMemoryChannelInfo (0, &DctChannel[0], Gfx);
+  if (NumberOfChannels == 2) {
+    GfxGmcDctMemoryChannelInfo (1, &DctChannel[1], Gfx);
+  }
+
+  // Find the Active Channels.  For a single channel system, Active channel is 0;
+  if (NumberOfChannels == 1) {
+    ActiveChannel = 0;
+  } else {
+    //For two channel system, Active channel could be either 0 or 1 or both (2)
+    if (DctChannel[0].D18F2x094.Field.DisDramInterface == 0 &&
+      DctChannel[1].D18F2x094.Field.DisDramInterface == 0) {
+      ActiveChannel = 2;
+    } else {
+      ActiveChannel = (DctChannel[0].D18F2x094.Field.DisDramInterface == 0) ? 0 : 1;
+    }
+  }
+
+  if (ActiveChannel == 2) {
+    // Both controllers enabled
+    GMMx277C.Field.ActRd = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5;
+    GMMx277C.Field.RasMActRd = MIN ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)),
+                                    (DctChannel[1].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[1].D18F2x0F4_x40.Field.Trcd + 5)));
+    GMMx2780.Field.Ras2Ras = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1;
+    GMMx2780.Field.Rp = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1;
+    GMMx2780.Field.WrPlusRp = MIN (
+                                ((DctChannel[0].D18F2x084.Field.Twr == 0) ? 16 :
+                                ((DctChannel[0].D18F2x084.Field.Twr < 4) ? (DctChannel[0].D18F2x084.Field.Twr + 4) :
+                                (DctChannel[0].D18F2x084.Field.Twr * 2)) + DctChannel[0].D18F2x0F4_x40.Field.Trp + 5),
+                                ((DctChannel[1].D18F2x084.Field.Twr == 0) ? 16 :
+                                ((DctChannel[1].D18F2x084.Field.Twr < 4) ? (DctChannel[1].D18F2x084.Field.Twr + 4) :
+                                (DctChannel[1].D18F2x084.Field.Twr * 2)) + DctChannel[1].D18F2x0F4_x40.Field.Trp + 5)
+                                ) - 1;
+    GMMx2780.Field.BusTurn = (MIN (
+                                DctChannel[0].D18F2x084.Field.Tcwl + 5 +
+                                DctChannel[0].D18F2x0F4_x41.Field.Twtr + 4 +
+                                DctChannel[0].D18F2x08C.Field.TrwtTO + 2 ,
+                                DctChannel[1].D18F2x084.Field.Tcwl + 5 +
+                                DctChannel[1].D18F2x0F4_x41.Field.Twtr + 4 +
+                                DctChannel[1].D18F2x08C.Field.TrwtTO + 2
+                                ) + 4) / 2;
+  } else {
+    // Only one channel is active.
+    GMMx277C.Field.ActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5;
+    GMMx277C.Field.RasMActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 -
+                              (DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5);
+    GMMx2780.Field.Ras2Ras = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 - 1;
+    GMMx2780.Field.Rp = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5 - 1;
+    GMMx2780.Field.WrPlusRp = ((DctChannel[ActiveChannel].D18F2x084.Field.Twr == 0) ? 16 :
+                              ((DctChannel[ActiveChannel].D18F2x084.Field.Twr < 4) ? (DctChannel[ActiveChannel].D18F2x084.Field.Twr + 4) :
+                               (DctChannel[ActiveChannel].D18F2x084.Field.Twr * 2)) +
+                               DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5) - 1;
+    GMMx2780.Field.BusTurn =  ((DctChannel[ActiveChannel].D18F2x084.Field.Tcwl + 5 +
+                                DctChannel[ActiveChannel].D18F2x0F4_x41.Field.Twtr + 4 +
+                                DctChannel[ActiveChannel].D18F2x08C.Field.TrwtTO + 2) + 4) / 2;
+  }
+  GMMx277C.Field.ActWr = GMMx277C.Field.ActRd;
+  GMMx277C.Field.RasMActWr = GMMx277C.Field.RasMActRd;
+
+  GmmRegisterWrite (
+    GMMx277C_ADDRESS,
+    GMMx277C.Value,
+    TRUE,
+    Gfx
+    );
+  GmmRegisterWrite (
+    GMMx28D8_ADDRESS,
+    GMMx277C.Value,
+    TRUE,
+    Gfx
+    );
+  GmmRegisterWrite (
+    GMMx2780_ADDRESS,
+    GMMx2780.Value,
+    TRUE,
+    Gfx
+    );
+    GmmRegisterWrite (
+    GMMx28DC_ADDRESS,
+    GMMx2780.Value,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Frame Buffer Location
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcInitializeFbLocation (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+ //Logical FB location
+  GMMx2024_STRUCT   GMMx2024;
+  GMMx2898_STRUCT   GMMx2898;
+  GMMx2C04_STRUCT   GMMx2C04;
+  GMMx5428_STRUCT   GMMx5428;
+  UINT64            FBBase;
+  UINT64            FBTop;
+  FBBase = 0x0F00000000ull;
+  FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1;
+  GMMx2024.Value = 0;
+  GMMx2898.Value = 0;
+  GMMx2C04.Value = 0;
+  GMMx5428.Value = 0;
+  GMMx2024.Field.Base = (UINT16) (FBBase >> 24);
+  GMMx2024.Field.Top = (UINT16) (FBTop >> 24);
+  GMMx2898.Field.Offset = (UINT32) (Gfx->UmaInfo.UmaBase >> 20);
+  GMMx2898.Field.Top = (UINT32) ((FBTop >> 20) & 0xf);
+  GMMx2898.Field.Base = (UINT32) ((FBBase >> 20) & 0xf);
+  GMMx2C04.Field.NonsurfBase = (UINT32) (FBBase >> 8);
+  GMMx5428.Field.ConfigMemsize = Gfx->UmaInfo.UmaSize;
+
+  GmmRegisterWrite (
+    GMMx2024_ADDRESS,
+    GMMx2024.Value,
+    TRUE,
+    Gfx
+    );
+  GmmRegisterWrite (
+    GMMx2898_ADDRESS,
+    GMMx2898.Value,
+    TRUE,
+    Gfx
+    );
+  GmmRegisterWrite (
+    GMMx2C04_ADDRESS,
+    GMMx2C04.Value,
+    TRUE,
+    Gfx
+    );
+  GmmRegisterWrite (
+    GMMx5428_ADDRESS,
+    GMMx5428.Value,
+    TRUE,
+    Gfx
+    );
+  GmmRegisterWriteField (
+    GMMx5490_ADDRESS,
+    GMMx5490_FbReadEn_OFFSET,
+    GMMx5490_FbReadEn_WIDTH,
+    1,
+    TRUE,
+    Gfx
+    );
+  GmmRegisterWriteField (
+    GMMx5490_ADDRESS,
+    GMMx5490_FbWriteEn_OFFSET,
+    GMMx5490_FbWriteEn_WIDTH,
+    1,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Secure Garlic Access
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcSecureGarlicAccess (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx286C_STRUCT   GMMx286C;
+  GMMx287C_STRUCT   GMMx287C;
+  GMMx2894_STRUCT   GMMx2894;
+  UINT32            Value;
+  GMMx286C.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20);
+  GmmRegisterWrite (GMMx286C_ADDRESS, GMMx286C.Value, TRUE, Gfx);
+  GMMx287C.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1);
+  GmmRegisterWrite (GMMx287C_ADDRESS, GMMx287C.Value, TRUE, Gfx);
+  // Areag FB - 20K reserved by VBIOS for SBIOS to use
+  GMMx2894.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 20 * 1024) >> 12);
+  GmmRegisterWrite (GMMx2894_ADDRESS, GMMx2894.Value, TRUE, Gfx);
+  Value = 0xfffff;
+  GmmRegisterWrite (GMMx2870_ADDRESS, Value, TRUE, Gfx);
+  GmmRegisterWrite (GMMx2874_ADDRESS, Value, TRUE, Gfx);
+  GmmRegisterWrite (GMMx2878_ADDRESS, Value, TRUE, Gfx);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Performance setting
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcPerformanceTuning (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GmmRegisterTableWrite (
+    GmcPerformanceTuningTablePtr.TablePtr,
+    GmcPerformanceTuningTablePtr.TableLength,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc. Initialization
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcMiscInit (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx2114_STRUCT  GMMx2114;
+
+  GMMx2114.Value = GmmRegisterRead (GMMx2114_ADDRESS, Gfx);
+  GMMx2114.Field.Stor1Pri = 0xC;
+  GmmRegisterWrite (GMMx2114_ADDRESS, GMMx2114.Value, TRUE, Gfx);
+
+  GmmRegisterTableWrite (
+    GmcMiscInitTablePtr.TablePtr,
+    GmcMiscInitTablePtr.TableLength,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lock critical registers
+ *
+ *
+ *
+ * @param[in] Gfx         Graphics configuration
+ */
+
+VOID
+GfxGmcLockCriticalRegisters (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GmmRegisterWriteField (
+    GMMx2B98_ADDRESS,
+    GMMx2B98_CriticalRegsLock_OFFSET,
+    GMMx2B98_CriticalRegsLock_WIDTH,
+    1,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Remove blackout
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+VOID
+GfxGmcRemoveBlackout (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GmmRegisterTableWrite (
+    GmcRemoveBlackoutTablePtr.TablePtr,
+    GmcRemoveBlackoutTablePtr.TableLength,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable clock Gating
+ *
+ *
+ *
+ * @param[in] Gfx         Graphics configuration
+ */
+
+VOID
+GfxGmcEnableClockGating (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GmmRegisterTableWrite (
+    GmcEnableClockGatingPtr.TablePtr,
+    GmcEnableClockGatingPtr.TableLength,
+    TRUE,
+    Gfx
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * UMA steering
+ *
+ *
+ *
+ * @param[in] Gfx         Graphics configuration
+ */
+
+VOID
+GfxGmcUmaSteering (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize C6 aperture
+ *
+ *
+ *
+ * @param[in] Gfx         Graphics configuration
+ */
+
+VOID
+GfxGmcInitializeC6Aperture (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D18F4x12C_STRUCT    D18F4x12C;
+  GMMx288C_STRUCT     GMMx288C;
+  GMMx2890_STRUCT     GMMx2890;
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 4, D18F4x12C_ADDRESS),
+    AccessWidth32,
+    &D18F4x12C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+  GMMx288C.Value = D18F4x12C.Field.C6Base_39_24_ << 4;
+  // Modify the values only if C6 Base is set
+  if (GMMx288C.Value != 0) {
+    GMMx2890.Value = (GMMx288C.Value + 16) - 1;
+    GmmRegisterWrite (
+      GMMx288C_ADDRESS,
+      GMMx288C.Value,
+      TRUE,
+      Gfx
+      );
+    GmmRegisterWrite (
+      GMMx2890_ADDRESS,
+      GMMx2890.Value,
+      TRUE,
+      Gfx
+      );
+  }
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Power Gating
+ *
+ *
+ *
+ * @param[in] Gfx         Graphics configuration
+ */
+
+VOID
+GfxGmcInitializePowerGating (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  switch (Gfx->GmcPowerGating) {
+  case  GmcPowerGatingDisabled:
+    break;
+  case  GmcPowerGatingStutterOnly:
+    GmmRegisterWriteField (
+      GMMx2B98_ADDRESS,
+      GMMx2B98_StctrlStutterEn_OFFSET,
+      GMMx2B98_StctrlStutterEn_WIDTH,
+      1,
+      TRUE,
+      Gfx
+      );
+    break;
+  case GmcPowerGatingWidthStutter:
+    GmmRegisterWriteField (
+      GMMx2B94_ADDRESS,
+      GMMx2B94_RengExecuteOnPwrUp_OFFSET,
+      GMMx2B94_RengExecuteOnPwrUp_WIDTH,
+      1,
+      TRUE,
+      Gfx
+      );
+    GmmRegisterWriteField (
+      GMMx2B98_ADDRESS,
+      GMMx2B98_RengExecuteOnRegUpdate_OFFSET,
+      GMMx2B98_RengExecuteOnRegUpdate_WIDTH,
+      1,
+      TRUE,
+      Gfx
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GMC
+ *
+ *
+ *
+ * @param[in] Gfx           Pointer to global GFX configuration
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxGmcInit (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Enter\n");
+  GfxGmcDisableClockGating (Gfx);
+  GfxGmcSetMemoryAddressTranslation (Gfx);
+  GfxGmcInitializeSequencerModel (Gfx);
+  GfxGmcInitializeRegisterEngine (Gfx);
+  GfxGmcInitializeFbLocation (Gfx);
+  GfxGmcUmaSteering (Gfx);
+  GfxGmcSecureGarlicAccess (Gfx);
+  GfxGmcInitializeC6Aperture (Gfx);
+  GfxFmGmcAddressSwizzel (Gfx);
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx));
+  GfxGmcLockCriticalRegisters (Gfx);
+  GfxGmcPerformanceTuning (Gfx);
+  GfxGmcMiscInit (Gfx);
+  GfxGmcRemoveBlackout (Gfx);
+  if (Gfx->GmcClockGating == OptionEnabled) {
+    GfxGmcEnableClockGating (Gfx);
+  }
+  GfxGmcInitializePowerGating (Gfx);
+  GfxFmGmcAllowPstateHigh (Gfx);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n");
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h
new file mode 100755
index 0000000000..d1d78a3f81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h
@@ -0,0 +1,55 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  GMC init services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXGMCINIT_H_
+#define _GFXGMCINIT_H_
+
+
+AGESA_STATUS
+GfxGmcInit (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c
new file mode 100755
index 0000000000..7855ce62e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c
@@ -0,0 +1,111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at env POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 48452 $   @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxConfig.h"
+#include  "GfxStrapsInit.h"
+#include  "GfxInitAtEnvPost.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXINITATENVPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Env Post.
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS
+  */
+
+
+AGESA_STATUS
+GfxInitAtEnvPost (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  if (Status == AGESA_SUCCESS) {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxStrapsInit (Gfx);
+      ASSERT (Status == AGESA_SUCCESS);
+    } else {
+      GfxDisableController (StdHeader);
+    }
+  } else {
+    GfxDisableController (StdHeader);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h
new file mode 100755
index 0000000000..1e429a6670
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h
@@ -0,0 +1,54 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at env POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXINITATENVPOST_H_
+#define _GFXINITATENVPOST_H_
+
+AGESA_STATUS
+GfxInitAtEnvPost (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c
new file mode 100755
index 0000000000..f7ea25b58b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c
@@ -0,0 +1,132 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at mid POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 51087 $   @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxConfig.h"
+#include  "GfxConfigData.h"
+#include  "GfxStrapsInit.h"
+#include  "GfxGmcInit.h"
+#include  "GfxInitAtMidPost.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxFamServices.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Mid Post.
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxInitAtMidPost (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status =  GfxLocateConfigData (StdHeader, &Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_FATAL) {
+    GfxDisableController (StdHeader);
+  } else {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxEnableGmmAccess (Gfx);
+      ASSERT (Status == AGESA_SUCCESS);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      if (Status != AGESA_SUCCESS) {
+        // Can not initialize GMM registers going to disable GFX controller
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Fail to establish GMM access\n");
+        Gfx->UmaInfo.UmaMode = UMA_NONE;
+        GfxDisableController (StdHeader);
+      } else {
+        Status = GfxGmcInit (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxSetBootUpVoltage (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxInitSsid (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      }
+    }
+    GfxFmSetIdleVoltageMode (Gfx);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h
new file mode 100755
index 0000000000..faad2f84c6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h
@@ -0,0 +1,55 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at mid POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXINITATMIDPOST_H_
+#define _GFXINITATMIDPOST_H_
+
+AGESA_STATUS
+GfxInitAtMidPost (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c
new file mode 100755
index 0000000000..0b4dc735dd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c
@@ -0,0 +1,124 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 48452 $   @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GfxStrapsInit.h"
+#include  "GfxLib.h"
+#include  "GfxConfigData.h"
+#include  "GfxInitAtPost.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXINITATPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Post.
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS
+ */
+
+
+AGESA_STATUS
+GfxInitAtPost (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_POST_PARAMS       *PostParamsPtr;
+  AGESA_STATUS          Status;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    if (GfxLibIsControllerPresent (StdHeader)) {
+      if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) {
+        GfxGetDiscreteCardInfo (&Gfx->GfxDiscreteCardInfo, StdHeader);
+        if (Gfx->GfxDiscreteCardInfo.PciGfxCardBitmap != 0 ||
+           (Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap & Gfx->GfxDiscreteCardInfo.PcieGfxCardBitmap) !=
+            Gfx->GfxDiscreteCardInfo.PcieGfxCardBitmap) {
+          PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+          IDS_HDT_CONSOLE (GFX_MISC, "  GfxDisabled due to dGPU policy\n");
+        }
+      }
+    } else {
+      PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+      Gfx->GfxFusedOff = TRUE;
+    }
+  } else {
+    PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h
new file mode 100755
index 0000000000..5b58629661
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h
@@ -0,0 +1,55 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXINITATPOST_H_
+#define _GFXINITATPOST_H_
+
+AGESA_STATUS
+GfxInitAtPost (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
new file mode 100755
index 0000000000..f9924f40b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
@@ -0,0 +1,701 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 48890 $   @e \$Date: 2011-03-14 14:32:00 +0800 (Mon, 14 Mar 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GfxLib.h"
+#include  "GfxConfigData.h"
+#include  "GfxRegisterAcc.h"
+#include  "GfxFamilyServices.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxIntegratedInfoTableInit.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT32
+GfxLibGetCsrPhySrPllPdMode (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibGetDisDllShutdownSR (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+
+
+ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = {
+  0x80040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00204080,
+  0x00204080,
+  0x0000001E,
+  0x00000000
+};
+
+
+ULONG ulCSR_M3_ARB_CNTL_UVD[] = {
+  0x80040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00204080,
+  0x00204080,
+  0x0000001E,
+  0x00000000
+};
+
+
+ULONG ulCSR_M3_ARB_CNTL_FS3D[] = {
+  0x80040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00040810,
+  0x00204080,
+  0x00204080,
+  0x0000001E,
+  0x00000000
+};
+
+
+VOID
+GfxIntegratedInfoInitDispclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxIntegratedInfoInitSclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxFillHtcData (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxFillNbPStateVid (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxFillM3ArbritrationControl (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+
+VOID
+GfxFillSbMmioBaseAddress (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxFillNclkInfo (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+AGESA_STATUS
+GfxIntegratedInfoTableInit (
+  IN      GFX_PLATFORM_CONFIG               *Gfx
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get CSR phy self refresh power down mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    CsrPhySrPllPdMode
+ */
+UINT32
+GfxLibGetCsrPhySrPllPdMode (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2x09C_x0D0FE00A_STRUCT     D18F2x09C_x0D0FE00A;
+
+  GnbLibCpuPciIndirectRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS),
+    D18F2x09C_x0D0FE00A_ADDRESS,
+    &D18F2x09C_x0D0FE00A.Value,
+    StdHeader
+    );
+
+  return  D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get disable DLL shutdown in self-refresh mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    DisDllShutdownSR
+ */
+UINT32
+GfxLibGetDisDllShutdownSR (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2x090_STRUCT D18F2x090;
+
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS),
+    AccessWidth32,
+    &D18F2x090.Value,
+    StdHeader
+    );
+
+  return  D18F2x090.Field.DisDllShutdownSR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *  GMC FB access requred
+ *
+ *
+ * @param[in]   StdHeader     Standard configuration header
+ * @retval      AGESA_STATUS
+ */
+AGESA_STATUS
+GfxIntegratedInfoTableEntry (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  AGESA_STATUS                    AgesaStatus;
+  AGESA_STATUS                    Status;
+  GFX_PLATFORM_CONFIG             *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  if (GfxLibIsControllerPresent (StdHeader)) {
+    Status = GfxLocateConfigData (StdHeader, &Gfx);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status != AGESA_FATAL) {
+      Status = GfxIntegratedInfoTableInit (Gfx);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Exit[0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *
+ *
+ *
+ * @param[in] Gfx             Gfx configuration info
+ * @retval    AGESA_STATUS
+ */
+AGESA_STATUS
+GfxIntegratedInfoTableInit (
+  IN      GFX_PLATFORM_CONFIG     *Gfx
+  )
+{
+  AGESA_STATUS                    Status;
+  AGESA_STATUS                    AgesaStatus;
+  ATOM_FUSION_SYSTEM_INFO_V1      SystemInfoV1Table;
+  PP_FUSE_ARRAY                   *PpFuseArray;
+  PCIe_PLATFORM_CONFIG            *Pcie;
+  UINT32                          IntegratedInfoAddress;
+  ATOM_PPLIB_POWERPLAYTABLE3      *PpTable;
+  UINT8                           Channel;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Enter\n");
+  LibAmdMemFill (&SystemInfoV1Table, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), GnbLibGetHeader (Gfx));
+  SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V6);
+  ASSERT (SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize == 512);
+  SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableContentRevision = 6;
+  SystemInfoV1Table.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetMainPllFreq (GnbLibGetHeader (Gfx)) * 100;
+  SystemInfoV1Table.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
+  SystemInfoV1Table.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
+  SystemInfoV1Table.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
+  SystemInfoV1Table.sIntegratedSysInfo.ucMemoryType = 3;     //DDR3
+  SystemInfoV1Table.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100;    //Set default engine clock to 200MhZ
+  SystemInfoV1Table.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
+  SystemInfoV1Table.sIntegratedSysInfo.ulMinEngineClock = GfxLibGetMinSclk (GnbLibGetHeader (Gfx));
+  SystemInfoV1Table.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
+
+  SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
+  SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate;
+  SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
+
+  //Locate PCIe configuration data to get definitions of display connectors
+  SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
+  SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
+  SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
+
+  ASSERT ((Gfx->UmaInfo.UmaAttributes & (UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1)) != 0);
+
+  if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
+    Channel = 0;
+  } else {
+    Channel = 1;
+  }
+  if (GfxLibGetCsrPhySrPllPdMode (Channel, GnbLibGetHeader (Gfx)) != 0) {
+    SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT2;
+  }
+  if (GfxLibGetDisDllShutdownSR (Channel, GnbLibGetHeader (Gfx)) == 0) {
+    SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT1;
+  }
+  Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    Status = GfxIntegratedEnumerateAllConnectors (
+               &SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
+               Pcie,
+               Gfx
+               );
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  SystemInfoV1Table.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V6, sExtDispConnInfo);
+  // Build PP table
+  PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoV1Table.ulPowerplayTable;
+  // Build PP table
+  Status = GfxPowerPlayBuildTable (PpTable,  Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  // Build info from fuses
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    // Build Display clock info
+    GfxIntegratedInfoInitDispclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+    // Build Sclk info table
+    GfxIntegratedInfoInitSclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  } else {
+    Status = AGESA_ERROR;
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  // Fill in HTC Data
+  GfxFillHtcData (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Fill in NB P states VID
+  GfxFillNbPStateVid (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Fill in NCLK info
+  GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Fill in the M3 arbitration control tables
+  GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Fill South bridge MMIO Base address
+  GfxFillSbMmioBaseAddress (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Family specific data update
+  GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoV1Table.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
+  //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
+  IntegratedInfoAddress = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V1));
+  GfxLibCopyMemToFb ((VOID *) (&SystemInfoV1Table), IntegratedInfoAddress, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), Gfx);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Dispclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxIntegratedInfoInitDispclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN   Index;
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->DisplclkDid[Index] != 0) {
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxLibCalculateClk (
+                                                                             PpFuseArray->DisplclkDid[Index],
+                                                                             IntegratedInfoTable->ulDentistVCOFreq
+                                                                             );
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Sclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxIntegratedInfoInitSclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN                       Index;
+  UINTN                       TargetIndex;
+  UINTN                       ValidSclkStateMask;
+  UINT8                       TempDID;
+  UINT8                       SclkVidArray[4];
+  UINTN                       AvailSclkIndex;
+  ATOM_AVAILABLE_SCLK_LIST    *AvailSclkList;
+  BOOLEAN                     Sorting;
+  AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0];
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
+    AccessWidth32,
+    &SclkVidArray[0],
+    GnbLibGetHeader (Gfx)
+    );
+  AvailSclkIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
+    if (PpFuseArray->SclkDpmDid[Index] != 0) {
+      AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], IntegratedInfoTable->ulDentistVCOFreq);
+      AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index];
+      AvailSclkList[AvailSclkIndex].usVoltageID = SclkVidArray [PpFuseArray->SclkDpmVid[Index]];
+      AvailSclkIndex++;
+    }
+  }
+  //Sort by VoltageIndex & ulSupportedSCLK
+  if (AvailSclkIndex > 1) {
+    do {
+      Sorting = FALSE;
+      for (Index = 0; Index < (AvailSclkIndex - 1); Index++) {
+        ATOM_AVAILABLE_SCLK_LIST  Temp;
+        BOOLEAN                   Exchange;
+        Exchange = FALSE;
+        if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) {
+          Exchange = TRUE;
+        }
+        if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) &&
+            (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) {
+          Exchange = TRUE;
+        }
+        if (Exchange) {
+          Sorting = TRUE;
+          LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+        }
+      }
+    } while (Sorting);
+  }
+
+  if (PpFuseArray->GpuBoostCap == 1) {
+    IntegratedInfoTable->SclkDpmThrottleMargin = PpFuseArray->SclkDpmThrottleMargin;
+    IntegratedInfoTable->SclkDpmTdpLimitPG = PpFuseArray->SclkDpmTdpLimitPG;
+    IntegratedInfoTable->EnableBoost = PpFuseArray->GpuBoostCap;
+    IntegratedInfoTable->SclkDpmBoostMargin = PpFuseArray->SclkDpmBoostMargin;
+    IntegratedInfoTable->SclkDpmTdpLimitBoost = (PpFuseArray->SclkDpmTdpLimit)[5];
+    IntegratedInfoTable->ulBoostEngineCLock = GfxFmCalculateClock ((PpFuseArray->SclkDpmDid)[5], GnbLibGetHeader (Gfx));
+    IntegratedInfoTable->ulBoostVid_2bit = (PpFuseArray->SclkDpmVid)[5];
+
+    ValidSclkStateMask = 0;
+    TargetIndex = 0;
+    for (Index = 0; Index < 6; Index++) {
+      ValidSclkStateMask |= (PpFuseArray->SclkDpmValid)[Index];
+    }
+    TempDID = 0x7F;
+    for (Index = 0; Index < 6; Index++) {
+      if ((ValidSclkStateMask & ((UINTN)1 << Index)) != 0) {
+        if ((PpFuseArray->SclkDpmDid)[Index] <= TempDID) {
+          TempDID = (PpFuseArray->SclkDpmDid)[Index];
+          TargetIndex = Index;
+        }
+      }
+    }
+    IntegratedInfoTable->GnbTdpLimit = (PpFuseArray->SclkDpmTdpLimit)[TargetIndex];
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init HTC Data
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxFillHtcData (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F3x64_STRUCT  D18F3x64;
+
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x64_ADDRESS),
+    AccessWidth32,
+    &D18F3x64.Value,
+    GnbLibGetHeader (Gfx)
+    );
+  IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52);
+  IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init NbPstateVid
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxFillNbPStateVid (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F3xDC_STRUCT  D18F3xDC;
+  D18F6x90_STRUCT  D18F6x90;
+
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS),
+    AccessWidth32,
+    &D18F3xDC.Value,
+    GnbLibGetHeader (Gfx)
+    );
+  IntegratedInfoTable->usNBP0Voltage = (USHORT) D18F3xDC.Field.NbPs0Vid;
+
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
+    AccessWidth32,
+    &D18F6x90.Value,
+    GnbLibGetHeader (Gfx)
+    );
+  IntegratedInfoTable->usNBP1Voltage = (USHORT) D18F6x90.Field.NbPs1Vid;
+  IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateClk (
+                                         (UINT8) (((D18F6x90.Field.NbPs1NclkDiv != 0) && (D18F6x90.Field.NbPs1NclkDiv < D18F3xDC.Field.NbPs0NclkDiv)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv),
+                                         IntegratedInfoTable->ulDentistVCOFreq
+                                         );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init M3 Arbitration Control values.
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxFillM3ArbritrationControl (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_DEFAULT, ulCSR_M3_ARB_CNTL_DEFAULT, sizeof (ulCSR_M3_ARB_CNTL_DEFAULT), GnbLibGetHeader (Gfx));
+  LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_UVD, ulCSR_M3_ARB_CNTL_UVD, sizeof (ulCSR_M3_ARB_CNTL_UVD), GnbLibGetHeader (Gfx));
+  LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_FS3D, ulCSR_M3_ARB_CNTL_FS3D, sizeof (ulCSR_M3_ARB_CNTL_FS3D), GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init M3 Arbitration Control values.
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxFillSbMmioBaseAddress (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  IntegratedInfoTable->ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx)) ;
+  IDS_HDT_CONSOLE (GFX_MISC, "  ulSB_MMIO_Base_Addr = 0x%x\n", IntegratedInfoTable->ulSB_MMIO_Base_Addr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Fill in NCLK info
+ *
+ * set ulMinimumNClk and ulIdleNClk
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+VOID
+GfxFillNclkInfo (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+
+  D18F3xA0_STRUCT  D18F3xA0;
+  D18F6x9C_STRUCT  D18F6x9C;
+  D18F3xDC_STRUCT  D18F3xDC;
+  D18F6x90_STRUCT  D18F6x90;
+
+  //
+  // ulIdleNClk = GfxLibGetMainPllFreq (...) / F6x9C[NclkRedDiv] divisor (main PLL frequency / NCLK divisor)
+  //
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x9C_ADDRESS),
+    AccessWidth32,
+    &D18F6x9C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  IntegratedInfoTable->ulIdleNClk = GfxLibCalculateIdleNclk (
+                                      (UINT8) D18F6x9C.Field.NclkRedDiv,
+                                      IntegratedInfoTable->ulDentistVCOFreq
+                                      );
+
+  //
+  // Set ulMinimumNClk depends on CPU fused and NB Pstate.
+  //
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS),
+    AccessWidth32,
+    &D18F3xA0.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  if (D18F3xA0.Field.CofVidProg) {
+
+    GnbLibPciRead (
+      MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS),
+      AccessWidth32,
+      &D18F3xDC.Value,
+      GnbLibGetHeader (Gfx)
+      );
+
+    GnbLibPciRead (
+      MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
+      AccessWidth32,
+      &D18F6x90.Value,
+      GnbLibGetHeader (Gfx)
+      );
+
+    //
+    // Set ulMinimumNClk if (F6x90[NbPsCap]==1 && F6x90[NbPsCtrlDis]==0) then  (
+    // GfxLibGetMainPllFreq (...) / F6x90[NbPs1NclkDiv] divisor
+    // ) else ( GfxLibGetMainPllFreq (...) / F3xDC[NbPs0NclkDiv] divisor
+    // )
+    //
+    IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateNclk (
+                                           (UINT8) (((D18F6x90.Field.NbPsCap == 1) && (D18F6x90.Field.NbPsCtrlDis == 0)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv),
+                                           IntegratedInfoTable->ulDentistVCOFreq
+                                           );
+  } else {
+    IntegratedInfoTable->ulMinimumNClk = 200 * 100;
+  }
+
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h
new file mode 100755
index 0000000000..bd784e31c5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h
@@ -0,0 +1,60 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 45310 $   @e \$Date: 2011-01-14 18:12:32 +0800 (Fri, 14 Jan 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXINTEGRATEDINFOTABLEINIT_H_
+#define _GFXINTEGRATEDINFOTABLEINIT_H_
+
+
+#define SB_IOMAP_REGCD6                   0x0CD6  // PM_Index
+#define SB_IOMAP_REGCD7                   0x0CD7  // PM_Data
+#define SB_MMIO_BASE_REG                  0x24    // PMIO register 0x24 has SB MMIO base
+#define SB_MMIO_DECODE_ENABLE             BIT0
+#define SB_MMIO_IO_MAPPED_ENABLE          BIT1
+
+AGESA_STATUS
+GfxIntegratedInfoTableEntry (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c
new file mode 100755
index 0000000000..e9fb5c0072
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c
@@ -0,0 +1,343 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize PP/DPM fuse table.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 50955 $   @e \$Date: 2011-04-16 04:51:05 +0800 (Sat, 16 Apr 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbFuseTable.h"
+#include  "GnbCommonLib.h"
+#include  "GfxLib.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate main PLL VCO
+ *
+ *
+ *
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    main PLL COF in Mhz
+ */
+
+UINT32
+GfxLibGetMainPllFreq (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32            MainPllFreq;
+  D18F3xD4_STRUCT   D18F3xD4;
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xD4_ADDRESS),
+    AccessWidth32,
+    &D18F3xD4.Value,
+    StdHeader
+    );
+  MainPllFreq = 100 * (D18F3xD4.Field.MainPllOpFreqId + 0x10);
+  return  MainPllFreq;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate clock from main VCO
+ *
+ *
+ *
+ * @param[in] Did           Fuse Divider
+ * @param[in] MainPllVco    Main Pll COF in 10KHz
+ * @retval                  Clock in 10KHz
+ */
+
+UINT32
+GfxLibCalculateClk (
+  IN      UINT8                   Did,
+  IN      UINT32                  MainPllVco
+  )
+{
+  UINT32  Divider;
+  if (Did >= 8 && Did <= 0x3F) {
+    Divider = Did * 25;
+  } else if (Did > 0x3F && Did <= 0x5F) {
+    Divider = (Did - 64) * 50 + 1600;
+  } else if (Did > 0x5F && Did <= 0x7E) {
+    Divider = (Did - 96) * 100 + 3200;
+  } else if (Did == 0x7f) {
+    Divider = 128 * 100;
+  } else {
+    ASSERT (FALSE);
+    return 200 * 100;
+  }
+  ASSERT (Divider != 0);
+  return (((MainPllVco * 100) + (Divider - 1)) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate did from main VCO
+ *
+ *
+ *
+ * @param[in] Vco           Vco in 10Khz
+ * @param[in] MainPllVco    Main Pll COF in 10Khz
+ * @retval                  DID
+ */
+
+UINT8
+GfxLibCalculateDid (
+  IN      UINT32                  Vco,
+  IN      UINT32                  MainPllVco
+  )
+{
+  UINT32  Divider;
+  UINT8   Did;
+  ASSERT (Vco != 0);
+  Divider = ((MainPllVco * 100) + (Vco - 1)) / Vco;
+  Did = 0;
+  if (Divider < 200) {
+  } else if (Divider <= 1575) {
+    Did = (UINT8) (Divider / 25);
+  } else if (Divider <= 3150) {
+    Did = (UINT8) ((Divider - 1600) / 50) + 64;
+  } else if (Divider <= 6200) {
+    Did = (UINT8) ((Divider - 3200) / 100) + 96;
+  } else {
+    Did = 0x7f;
+  }
+  return Did;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max non 0 VID index
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID index
+ */
+UINT8
+GfxLibMaxVidIndex (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8           MaxVid;
+  UINT8           MaxVidIndex;
+  UINT8           SclkVidArray[4];
+  UINTN           Index;
+
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
+    AccessWidth32,
+    &SclkVidArray[0],
+    StdHeader
+    );
+  MaxVidIndex = 0;
+  MaxVid = 0xff;
+  for (Index = 0; Index < 4; Index++) {
+    if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < MaxVid) {
+      MaxVid = SclkVidArray[Index];
+      MaxVidIndex = (UINT8) Index;
+    }
+  }
+  return MaxVidIndex;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get min SCLK
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    Min SCLK in 10 khz
+ */
+UINT32
+GfxLibGetMinSclk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32  WrCkClk;
+  UINT32  MinSclkClk;
+  WrCkClk = GfxLibGetWrCk (StdHeader);
+
+  if ((2 * WrCkClk) < (8 * 100)) {
+    MinSclkClk = 8 * 100;
+  } else {
+    MinSclkClk = 2 * WrCkClk + 100;
+  }
+  return MinSclkClk;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get min WRCK
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    Min WRCK in 10 khZ
+ */
+UINT32
+GfxLibGetWrCk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PP_FUSE_ARRAY   *PpFuseArray;
+  UINT8           WrCk;
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    if (PpFuseArray->WrCkDid == 0x0) {
+      WrCk = 2;
+    } else if (PpFuseArray->WrCkDid <= 0x10) {
+      WrCk = PpFuseArray->WrCkDid + 1;
+    } else if (PpFuseArray->WrCkDid <= 0x1C) {
+      WrCk = 24 + 8 * (PpFuseArray->WrCkDid - 0x10);
+    } else {
+      WrCk = 128;
+    }
+  } else {
+    WrCk = 2;
+  }
+  return 100 * 100 / WrCk;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate NCLK clock from main VCO
+ *
+ *
+ *
+ * @param[in] Did           NCLK Divider
+ * @param[in] MainPllVco    Main Pll COF in 10KHz
+ * @retval                  Clock in 10KHz
+ */
+
+UINT32
+GfxLibCalculateNclk (
+  IN      UINT8                   Did,
+  IN      UINT32                  MainPllVco
+  )
+{
+  UINT32  Divider;
+  if (Did >= 8 && Did <= 0x3F) {
+    Divider = Did * 25;
+  } else if (Did > 0x3F && Did <= 0x5F) {
+    Divider = (Did - 64) * 50 + 1600;
+  } else if (Did > 0x5F && Did <= 0x7F) {
+    Divider = (Did - 64) * 100;
+  } else {
+    ASSERT (FALSE);
+    return 200 * 100;
+  }
+  ASSERT (Divider != 0);
+  return ((MainPllVco * 100) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate idle NCLK clock from main VCO
+ *
+ *
+ *
+ * @param[in] Did           NCLK Divider
+ * @param[in] MainPllVco    Main Pll COF in 10KHz
+ * @retval                  Clock in 10KHz
+ */
+
+UINT32
+GfxLibCalculateIdleNclk (
+  IN      UINT8                   Did,
+  IN      UINT32                  MainPllVco
+  )
+{
+  UINT32  Divider;
+  switch (Did) {
+  case 0x20:
+    Divider = 8;
+    break;
+  case 0x40:
+    Divider = 16;
+    break;
+  case 0x60:
+    Divider = 32;
+    break;
+  case 0x78:
+    Divider = 56;
+    break;
+  case 0x7F:
+    Divider = 128;
+    break;
+  default:
+    ASSERT (FALSE);
+    return 200 * 100;
+    break;
+  }
+
+  return (MainPllVco / Divider);
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h
new file mode 100755
index 0000000000..625a3b3ad3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXLIB_H_
+#define _GFXLIB_H_
+
+UINT32
+GfxLibGetMainPllFreq (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibCalculateClk (
+  IN      UINT8                   Did,
+  IN      UINT32                  MainPllVco
+  );
+
+UINT8
+GfxLibCalculateDid (
+  IN      UINT32                  Vco,
+  IN      UINT32                  MainPllVco
+  );
+
+UINT8
+GfxLibMaxVidIndex (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+UINT32
+GfxLibGetMinSclk (
+  IN      AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibGetWrCk (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+UINT32
+GfxLibCalculateNclk (
+  IN      UINT8                   Did,
+  IN      UINT32                  MainPllVco
+  );
+
+UINT32
+GfxLibCalculateIdleNclk (
+  IN      UINT8                   Did,
+  IN      UINT32                  MainPllVco
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c
new file mode 100755
index 0000000000..8f73921c43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c
@@ -0,0 +1,208 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics controller access service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 48452 $   @e \$Date: 2011-03-09 12:50:44 +0800 (Wed, 09 Mar 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GfxRegisterAcc.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXREGISTERACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GMM register
+ *
+ *
+ * @param[in] Address         GMM register address
+ * @param[in] Value           Value
+ * @param[in] S3Save          Save for S3 resume
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+GmmRegisterWrite (
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ASSERT (Gfx->GmmBase != 0);
+  GnbLibMemWrite (Gfx->GmmBase + Address, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read GMM register
+ *
+ *
+ * @param[in] Address         GMM register address
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval                    Value of GMM register
+ */
+
+UINT32
+GmmRegisterRead (
+  IN      UINT16                Address,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32  Value;
+  ASSERT (Gfx->GmmBase != 0);
+  GnbLibMemRead (Gfx->GmmBase + Address, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GMM register field
+ *
+ *
+ * @param[in] Address         GMM register address
+ * @param[in] FieldOffset     Register field offset
+ * @param[in] FieldWidth      Register field width
+ * @param[in] Value           Field value
+ * @param[in] S3Save          Save for S3 resume
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+GmmRegisterWriteField (
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32  Data;
+  UINT32  Mask;
+  Data = GmmRegisterRead (Address, Gfx);
+  Mask = (1 << FieldWidth) - 1;
+  Value &= Mask;
+  Data &= (~(Mask << FieldOffset));
+  GmmRegisterWrite (Address, Data | (Value << FieldOffset), S3Save, Gfx);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GMM registers table
+ *
+ *
+ * @param[in] Table           Pointer to table
+ * @param[in] TableLength     Number of entries in table
+ * @param[in] S3Save          Save for S3 resume
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+
+VOID
+GmmRegisterTableWrite (
+  IN      GMM_REG_ENTRY         Table[],
+  IN      UINTN                 TableLength,
+  IN      BOOLEAN               S3Save,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINTN Index;
+  for (Index = 0; Index < TableLength; Index++) {
+    GmmRegisterWrite (Table[Index].GmmReg, Table[Index].GmmData, S3Save, Gfx);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy memory content to FB
+ *
+ *
+ * @param[in] Source       Pointer to source
+ * @param[in] FbOffset     FB offset
+ * @param[in] Length       The length to copy
+ * @param[in] Gfx          Pointer to global GFX configuration
+ *
+ */
+VOID
+GfxLibCopyMemToFb (
+  IN     VOID                   *Source,
+  IN     UINT32                  FbOffset,
+  IN     UINT32                  Length,
+  IN     GFX_PLATFORM_CONFIG    *Gfx
+  )
+{
+  GMMx00_STRUCT GMMx00;
+  GMMx04_STRUCT GMMx04;
+  UINT32        Index;
+  for (Index = 0; Index < Length; Index = Index + 4 ) {
+    GMMx00.Value = 0x80000000 | (FbOffset + Index);
+    GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index);
+    GmmRegisterWrite (GMMx00_ADDRESS, GMMx00.Value, FALSE, Gfx);
+    GmmRegisterWrite (GMMx04_ADDRESS, GMMx04.Value, FALSE, Gfx);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h
new file mode 100755
index 0000000000..2194da2e6c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h
@@ -0,0 +1,112 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics controller access service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXREGISTERACC_H_
+#define _GFXREGISTERACC_H_
+
+/// GMM Register Entry
+typedef struct {
+  UINT16  GmmReg;             ///< Register
+  UINT32  GmmData;            ///< Data
+} GMM_REG_ENTRY;
+
+/// Register to Register copy
+typedef struct {
+  UINT32  CpuReg;             ///< CPU Register
+  UINT16  GmmReg;             ///< GMM Register
+  UINT8   CpuOffset;          ///< CPU register field start bit
+  UINT8   CpuWidth;           ///< CPU register field width
+  UINT8   GmmOffset;          ///< GMM register field start bit
+  UINT8   GmmWidth;           ///< GMM register field width
+} REGISTER_COPY_ENTRY;
+
+
+/// Table length and table pointer
+typedef struct {
+  UINT32  TableLength;        ///< Table Length
+  VOID*   TablePtr;           ///< Table Pointer
+} TABLE_INDIRECT_PTR;
+
+VOID
+GmmRegisterWrite (
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+UINT32
+GmmRegisterRead (
+  IN      UINT16                Address,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GmmRegisterWriteField (
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+
+VOID
+GmmRegisterTableWrite (
+  IN      GMM_REG_ENTRY         Table[],
+  IN      UINTN                 TableLength,
+  IN      BOOLEAN               S3Save,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxLibCopyMemToFb (
+  IN     VOID                   *Source,
+  IN     UINT32                  FbOffset,
+  IN     UINT32                  Length,
+  IN     GFX_PLATFORM_CONFIG    *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c
new file mode 100755
index 0000000000..3dcf763dc7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c
@@ -0,0 +1,271 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics controller BIF straps control services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 51087 $   @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+//#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GfxStrapsInit.h"
+#include  "GfxLib.h"
+#include  "GfxRegisterAcc.h"
+#include  "NbSmuLib.h"
+#include  "OptionGnb.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+extern GNB_BUILD_OPTIONS GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize GFX straps.
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxStrapsInit (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D0F0x64_x1C_STRUCT  D0F0x64_x1C;
+  D0F0x64_x1D_STRUCT  D0F0x64_x1D;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Enter\n");
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0;
+  D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0;
+
+  if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
+    D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x0;
+    D0F0x64_x1C.Field.RcieEn = 0x0;
+    D0F0x64_x1C.Field.PcieDis = 0x1;
+  } else {
+    D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1;
+    D0F0x64_x1C.Field.RcieEn = 0x1;
+    D0F0x64_x1C.Field.PcieDis = 0x0;
+    //LN/ON A0 (MSI)
+    GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessS3SaveWidth32, 0xffffffff, BIT2, GnbLibGetHeader (Gfx));
+  }
+  if (Gfx->ForceGfxMode == GfxEnableForceSecondary) {
+    D0F0x64_x1D.Field.VgaEn = 0x0;
+  } else {
+    D0F0x64_x1D.Field.VgaEn = 0x1;
+  }
+  D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio;
+  D0F0x64_x1C.Field.F0En = 0x1;
+  D0F0x64_x1C.Field.RegApSize = 0x1;
+
+  if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x1;
+  } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x0;
+  } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x2;
+  } else {
+    D0F0x64_x1C.Field.MemApSize = 0x3;
+  }
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.WriteDis = 0x1;
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Exit\n");
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable integrated GFX controller
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GfxDisableController (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  FCRxFF30_0AE6_STRUCT       FCRxFF30_0AE6;
+  D18F6x90_STRUCT            D18F6x90;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Enter\n");
+  GnbLibPciRMW (
+    GNB_SBDFO | D0F0x7C_ADDRESS,
+    AccessS3SaveWidth32,
+    0xffffffff,
+    1 << D0F0x7C_ForceIntGFXDisable_OFFSET,
+    StdHeader
+    );
+
+  // With iGPU is disabled, Program D18F6x90[NbPs1GnbSlowIgn]=1
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
+    AccessWidth32,
+    &D18F6x90.Value,
+    StdHeader
+    );
+  D18F6x90.Field.NbPs1GnbSlowIgn = 0x1;
+  GnbLibPciWrite (
+    MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
+    AccessWidth32,
+    &D18F6x90.Value,
+    StdHeader
+    );
+
+  // With iGPU is disabled, Enable stutter without gmc power gating.
+  NbSmuSrbmRegisterRead (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, StdHeader);
+  FCRxFF30_0AE6.Field.StctrlStutterEn = 0x1;
+  NbSmuSrbmRegisterWrite (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, TRUE, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Exit\n");
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Request GFX boot up voltage
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxSetBootUpVoltage (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx770_STRUCT  GMMx770;
+  GMMx774_STRUCT  GMMx774;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Enter\n");
+
+  GMMx770.Value = GmmRegisterRead (GMMx770_ADDRESS, Gfx);
+  GMMx770.Field.VoltageChangeEn = 1;
+  GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx);
+  GMMx770.Field.VoltageLevel = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
+  GMMx770.Field.VoltageChangeReq = !GMMx770.Field.VoltageChangeReq;
+  GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx);
+  do {
+    GMMx774.Value = GmmRegisterRead (GMMx774_ADDRESS, Gfx);
+  } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set idle voltage mode for GFX
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+GfxSetIdleVoltageMode (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h
new file mode 100755
index 0000000000..196444faee
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h
@@ -0,0 +1,77 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics controller BIF straps control services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 51087 $   @e \$Date: 2011-04-19 07:38:57 +0800 (Tue, 19 Apr 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+
+#ifndef _GFXSTRAPSINIT_H_
+#define _GFXSTRAPSINIT_H_
+
+AGESA_STATUS
+GfxInitSsid (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+AGESA_STATUS
+GfxStrapsInit (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxDisableController (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+
+AGESA_STATUS
+GfxSetBootUpVoltage (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+VOID
+GfxSetIdleVoltageMode (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+#endif
+