diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2014-01-25 15:59:31 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-07 17:40:45 +0100 |
| commit | 2e0d9447db22183e2d3393d84e221e8bb1613d45 (patch) | |
| tree | d481c26efa3b5501505f116226d747dd36d730a3 /src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c | |
| parent | f8532b16bec1743b0528a215c71f67c8845e2a0c (diff) | |
src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c')
| -rw-r--r-- | src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c index 1bad891b89..57483a9b15 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c @@ -148,7 +148,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); } - // restore variable MTTR6 and MTTR7 to default states + // restore variable MTRR6 and MTRR7 to default states for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared __writemsr (msrno, 0); |