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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-24 08:18:26 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-28 14:36:28 +0000
commite363894d066fe33e826847b3cc4a32a04587d080 (patch)
treec8239d44ce1facec6308a4c34d945655a94a5fa4 /src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3
parente029c18f67f72fc5542254c58d2d4d9025f6282f (diff)
AGESA f10 vendorcode: Remove refcode sources
We never had a board in the tree that implements this. Change-Id: Idce32a20c24e31eb52f8509d4a7cccfc24cf17cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3')
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c223
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h135
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c167
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h90
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c307
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h87
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c521
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h86
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c1089
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h166
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c161
-rw-r--r--src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c603
12 files changed, 0 insertions, 3635 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c
deleted file mode 100644
index b0f9a36c13..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
- * @file
- *
- * mt3.c
- *
- * Common Technology functions for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mtspd3.h"
-#include "mtot3.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-/* features */
-#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function Constructs the technology block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemConstructTechBlock3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- TECHNOLOGY_TYPE *TechTypePtr;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 DimmSlots;
-
-
- TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0);
- if (TechTypePtr != NULL) {
- // Ensure the platform override value is valid
- ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
- if (*TechTypePtr != DDR3_TECHNOLOGY) {
- return FALSE;
- }
- }
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- TechPtr->SendAllMRCmds = MemTSendAllMRCmds3;
- TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3;
- TechPtr->SetDramMode = MemTSetDramMode3;
- TechPtr->DimmPresence = MemTDIMMPresence3;
- TechPtr->SpdCalcWidth = MemTSPDCalcWidth3;
- TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3;
- TechPtr->AutoCycTiming = MemTAutoCycTiming3;
- TechPtr->SpdSetBanks = MemTSPDSetBanks3;
- TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
- TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3;
- TechPtr->AdjustTwrwr = MemTAdjustTwrwr3;
- TechPtr->AdjustTwrrd = MemTAdjustTwrrd3;
- TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3;
- TechPtr->GetLD = MemTGetLD3;
- TechPtr->MaxFilterDly = 0;
-
- //
- // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
- // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
- //
- // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
- // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
- // on this array only)
- // 2 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // DimmSpdPtr[2]------->NULL
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // | DimmSpdPtr[2]------->NULL
- // +----DimmSpdPtr[3]
- //
- // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
- // +-- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- // 3 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- //
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->TechType = DDR3_TECHNOLOGY;
- ChannelPtr->MCTPtr = MCTPtr;
- ChannelPtr->DCTPtr = DCTPtr;
-
- DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- //
- // Initialize the SPD pointers for each Dimm
- //
- for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
- ChannelPtr->DimmSpdPtr[i] = NULL;
- }
- for (i = 0 ; i < DimmSlots; i++) {
- ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
- if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
- if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
- if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) {
- ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
- }
- }
- }
- }
- }
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h
deleted file mode 100644
index 4470e38ad9..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/**
- * @file
- *
- * mt3.h
- *
- * Common Technology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 6608 $ @e \$Date: 2008-07-02 17:00:59 -0500 (Wed, 02 Jul 2008) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MT3_H_
-#define _MT3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructTechBlock3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-BOOLEAN
-MemTSetDramMode3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTDIMMPresence3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDCalcWidth3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDGetTargetSpeed3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTAutoCycTiming3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDSetBanks3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTGetCSIntLvAddr3 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- );
-
-VOID
-MemTSendAllMRCmds3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- );
-
-VOID
-FreqChgCtrlWrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-
-BOOLEAN
-MemTGetDimmSpdBuffer3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- );
-
-#endif /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c
deleted file mode 100644
index 8058ebda0f..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
- * @file
- *
- * mtot3.c
- *
- * Technology Non-SPD Timings for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtot3.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrwr value for DDR3.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrwr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved.
- if (DCTPtr->Timings.Twrwr < 2) {
- DCTPtr->Timings.Twrwr = 2;
- } else if (DCTPtr->Timings.Twrwr > 10) {
- DCTPtr->Timings.Twrwr = 10;
- }
- IDS_HDT_CONSOLE ("@\tTwrwr: %d for Socket %d, Die %d, Channel %d\n", DCTPtr->Timings.Twrwr, TechPtr->NBPtr->MCTPtr->SocketId, \
- TechPtr->NBPtr->Node, TechPtr->NBPtr->Dct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrrd value for DDR3.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved.
- if (DCTPtr->Timings.Twrrd < 2) {
- DCTPtr->Timings.Twrrd = 2;
- } else if (DCTPtr->Timings.Twrrd > 10) {
- DCTPtr->Timings.Twrrd = 10;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets the LD value for DDR3.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return Value of LD
- */
-
-INT8
-MemTGetLD3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- INT8 LD;
- MEM_NB_BLOCK *NBPtr;
- NBPtr = TechPtr->NBPtr;
- //
- // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
- // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
- // value.
- //
- LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5);
-
- return LD;
-}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h
deleted file mode 100644
index 6a66971329..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- * @file
- *
- * mtot3.h
- *
- * Technology Non-SPD timings for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTOT3_H_
-#define _MTOT3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-VOID
-MemTAdjustTwrwr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTAdjustTwrrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-INT8
-MemTGetLD3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
deleted file mode 100644
index 77ddfb4f43..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- * @file
- *
- * mtrci3.c
- *
- * Technology Control word initialization for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mtrci3.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTSendCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CmdNum,
- IN UINT8 Value
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends control words
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTDramControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 ChipSel;
- UINT8 i;
- UINT8 RawCard;
- UINT8 Data;
- UINT16 CsPresent;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
-
- MemUWait10ns (800, MemPtr); // wait 8us TACT must be changed to optimize to 8 MEM CLKs
-
- // Set EnDramInit to start DRAM initialization
-
- MemUWait10ns (600, MemPtr); // wait 6us for PLL LOCK
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- //
- // If chip select present
- //
- if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
-
- // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
-
- RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1];
-
- for (i = 0; i <= 15; i++) {
- // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
- MemUWait10ns (800, MemPtr);
- if ((i != 6) && (i != 7)) {
- Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel);
- MemTSendCtlWord3 (TechPtr, i, Data);
- }
- }
- }
- }
- MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the ControlRC value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] CtrlWordNum - control Word number.
- * @param[in] RawCard - Raw Card
- * @param[in] ChipSel - Target Chip Select
- * @return Control Word value
- */
-
-UINT8
-MemTGetCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CtrlWordNum,
- IN UINT8 RawCard,
- IN UINT8 ChipSel
- )
-{
- UINT8 Data;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Data = 0; //Default value for all control words is 0
- switch (CtrlWordNum) {
- case 0:
- Data = 0x02; // DA4=1
- break;
- case 1:
- if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) {
- Data = 0x0C; // if single rank, set DBA1 and DBA0
- }
- break;
- case 2:
- Data = ChannelPtr->CtrlWrd02[ChipSel >> 1];
- break;
- case 3:
- Data = ChannelPtr->CtrlWrd03[ChipSel >> 1];
- break;
- case 4:
- Data = ChannelPtr->CtrlWrd04[ChipSel >> 1];
- break;
- case 5:
- Data = ChannelPtr->CtrlWrd05[ChipSel >> 1];
- break;
- case 8:
- Data = ChannelPtr->CtrlWrd08[ChipSel >> 1];
- break;
- case 9:
- Data = 0x0D;
- break;
- default:;
- }
-
- return (Data & 0x0F);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends control word command
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] CmdNum - control number.
- * @param[in] Value - value to send
- *
- */
-
-VOID
-STATIC
-MemTSendCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CmdNum,
- IN UINT8 Value
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // 1. Program MrsBank and MrsAddress.
- // n = [BA2, A2, A1, A0].
- // data = [BA1, BA0, A4, A3].
- // Set all other bits in MrsAddress to zero.
- //
- NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2));
- NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7));
- IDS_HDT_CONSOLE ("\t\tCS%lx RC%02lx %04lx\n",
- (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 15) & 8) |
- (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) & 7),
- ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 14) & 0xC) |
- ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 3) & 3));
-
- // 2.Set SendCtrlWord=1
- NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1);
- // 3.Wait for BFSendCtrlWord=0
- NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends specific control words commands before frequency change for certain DRAM buffers.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-FreqChgCtrlWrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 ChipSel;
- UINT16 Speed;
- UINT16 CsPresent;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- Speed = NBPtr->DCTPtr->Timings.Speed;
- CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
-
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- //
- // If chip select present.
- //
- if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
-
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
- // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
-
- //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
- MemUWait10ns (800, MemPtr);
- if (Speed == DDR1066_FREQUENCY) {
- MemTSendCtlWord3 (TechPtr, 0x0A, 1);
- } else if (Speed == DDR1333_FREQUENCY) {
- MemTSendCtlWord3 (TechPtr, 0x0A, 2);
- } else if (Speed == DDR1600_FREQUENCY) {
- MemTSendCtlWord3 (TechPtr, 0x0A, 3);
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h
deleted file mode 100644
index fd558e6519..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * @file
- *
- * mtrci3.h
- *
- * Technology control word init for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTRCI3_H_
-#define _MTRCI3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-UINT8
-MemTGetCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CtrlWordNum,
- IN UINT8 RawCard,
- IN UINT8 ChipSel
- );
-
-VOID
-MemTDramControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c
deleted file mode 100644
index f938413a29..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/**
- * @file
- *
- * mtsdi3.c
- *
- * Technology Software DRAM Init for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mtsdi3.h"
-#include "mtrci3.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_TECH_DDR3_MTSDI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTEMRS33 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-STATIC
-MemTMRS3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates software DRAM init for both DCTs
- * at the same time.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemTDramInitSw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 ChipSel;
- UINT32 Dummy;
-
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- IDS_HDT_CONSOLE ("!\nStart Dram Init\n");
- // 3.Program F2x[1,0]7C[EnDramInit]=1
- IDS_HDT_CONSOLE ("\tEnDramInit = 1 for both DCTs\n");
- NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 1);
- NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
-
- // 4.wait 200us
- MemUWait10ns (20000, MemPtr);
-
- // 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1.
- NBPtr->BrdcstSet (NBPtr, BFDeassertMemRstX, 1);
-
- // 6.wait 500us
- MemUWait10ns (50000, MemPtr);
-
- // Do Phy Fence training before sending MRS commands
- if (!NBPtr->IsSupported[FenceTrnBeforeDramInit]) {
- AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
- NBPtr->PhyFenceTraining (NBPtr);
- }
- }
- }
-
- // 7.NOP or deselect & take CKE high
- NBPtr->BrdcstSet (NBPtr, BFAssertCke, 1);
-
- // 8.wait 360ns
- MemUWait10ns (36, MemPtr);
-
- // The following steps are performed once for each channel with unbuffered DIMMs
- // and once for each chip select on registered DIMMs:
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
- // The following steps are performed with registered DIMMs only and
- // must be done for each chip select pair:
- if (MCTPtr->Status[SbRegistered]) {
- MemTDramControlRegInit3 (TechPtr);
- }
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) {
- IDS_HDT_CONSOLE ("!\t\tCS %d\n", ChipSel);
- // if chip select present
- MemTSendAllMRCmds3 (TechPtr, ChipSel);
- // NOTE: wait 512 clocks for DLL-relock
- MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us
- if (!MCTPtr->Status[SbRegistered]) {
- break;
- }
- }
- }
-
- // 17.Send two ZQCL commands (to even then odd chip select)
- NBPtr->sendZQCmd (NBPtr);
- NBPtr->sendZQCmd (NBPtr);
- }
- }
-
- // 18.Program F2x[1,0]7C[EnDramInit]=0
- NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 0);
- NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
- //
- // For Unbuffered Dimms, Issue MRS for remaining CS without EnDramInit
- //
- if (!MCTPtr->Status[SbRegistered]) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) {
- IDS_HDT_CONSOLE ("!\t\tCS %d\n", ChipSel);
- // if chip select present
- MemTSendAllMRCmds3 (TechPtr, ChipSel);
- // NOTE: wait 512 clocks for DLL-relock
- MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us
- }
- }
- }
- }
- }
-
-
- IDS_HDT_CONSOLE ("End Dram Init\n\n");
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS1 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Wl - Indicates if WL mode should be enabled
- * @param[in] TargetDIMM - DIMM target for WL
- */
-
-VOID
-MemTEMRS13 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN BOOLEAN Wl,
- IN UINT8 TargetDIMM
- )
-{
- UINT16 MrsAddress;
- UINT8 MaxDimmPerCH;
- UINT8 ChipSel;
- UINT8 Value8;
-
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- NBPtr->ChannelPtr->ChannelID);
- ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
-
- // BA2=0,BA1=0,BA0=1
- NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
-
- MrsAddress = 0;
-
- // program MrsAddress[5,1]=output driver impedance control (DIC):
- // based on F2x[1,0]84[DrvImpCtrl]
- Value8 = (UINT8)NBPtr->GetBitField (NBPtr, BFDrvImpCtrl);
- if ((Value8 & ((UINT8) 1 << 1)) != 0) {
- MrsAddress |= ((UINT16) 1 << 5);
- }
- if ((Value8 & ((UINT8) 1 << 0)) != 0) {
- MrsAddress |= ((UINT16) 1 << 1);
- }
-
- // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
- // Different CS may have different RTT.
- //
- if (NBPtr->MCTPtr->Status[SbRegistered]) {
- //
- // Registered Dimms
- //
- if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT16) (1 << (ChipSel >> 1)))) != 0) {
- Value8 = NBPtr->PsPtr->QR_DramTerm;
- } else {
- Value8 = NBPtr->PsPtr->DramTerm;
- }
- } else {
- //
- // Unbuffered Dimms
- //
- Value8 = NBPtr->PsPtr->DramTerm;
- }
- //
- // If Write Leveling this DIMM
- //
- if (Wl) {
- if ((ChipSel >> 1) == TargetDIMM) {
- // Program MrsAddress[7] = 1 for Write leveling enable
- MrsAddress |= ((UINT16) 1 << 7);
- if (ChipSel & 1) {
- // Output buffer disabled, MrsAddress[7] (Qoff = 1)
- MrsAddress |= ((UINT16) 1 << 12);
- }
- // Set Rtt_Nom = Rtt_Wr if there are 2 or more dimms
- if ((NBPtr->ChannelPtr->DimmQrPresent != 0) || (NBPtr->ChannelPtr->Dimms >= 2)) {
- Value8 = NBPtr->PsPtr->DynamicDramTerm;
- }
- }
- }
- //
- // Turn off Rtt_Nom (DramTerm=0) for certain CS in certain configs.
- //
- // All odd CS for 4 Dimm Systems
- if (MaxDimmPerCH == 4) {
- if (ChipSel & 0x01) {
- Value8 = 0;
- }
- // CS 1 and 5 for 3 Dimm configs
- } else if (MaxDimmPerCH == 3) {
- if ((ChipSel == 1) || (ChipSel == 5)) {
- Value8 = 0;
- }
- }
- // All odd CS of any QR Dimms
- if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
- if (ChipSel & 0x01) {
- Value8 = 0;
- }
- }
- if ((Value8 & ((UINT8) 1 << 2)) != 0) {
- MrsAddress |= ((UINT16) 1 << 9);
- }
- if ((Value8 & ((UINT8) 1 << 1)) != 0) {
- MrsAddress |= ((UINT16) 1 << 6);
- }
- if ((Value8 & ((UINT8) 1 << 0)) != 0) {
- MrsAddress |= ((UINT16) 1 << 2);
- }
-
- // program MrsAddress[12]=output disable (QOFF):
- // based on F2x[1,0]84[Qoff]
- if (NBPtr->GetBitField (NBPtr, BFQoff) != 0) {
- MrsAddress |= ((UINT16) 1 << 12);
- }
-
- // program MrsAddress[11]=TDQS:
- // based on F2x[1,0]94[RDqsEn]
- if (NBPtr->GetBitField (NBPtr, BFRDqsEn) != 0) {
- MrsAddress |= ((UINT16) 1 << 11);
- }
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS2 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTEMRS23 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT32 MrsAddress;
- UINT8 DramTermDyn;
- UINT8 MaxDimmPerCH;
- UINT8 ChipSel;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID );
- ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
-
- // BA2=0,BA1=1,BA0=0
- NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
-
- // program MrsAddress[5:3]=CAS write latency (CWL):
- // based on F2x[1,0]84[Tcwl]
- MrsAddress = NBPtr->GetBitField (NBPtr, BFTcwl) << 3;
-
- // program MrsAddress[6]=auto self refresh method (ASR):
- // based on F2x[1,0]84[ASR]
- // program MrsAddress[7]=self refresh temperature range (SRT):
- // based on F2x[1,0]84[ASR and SRT]
- MrsAddress |= NBPtr->GetBitField (NBPtr, BFASR) << 6;
- MrsAddress |= NBPtr->GetBitField (NBPtr, BFSRT) << 7;
-
- // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
- // based on F2x[1,0]84[DramTermDyn]
- DramTermDyn = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTermDyn);
- // Special Case for 1 DR Unbuffered Dimm in 3 Dimm/Ch
- if (!(NBPtr->MCTPtr->Status[SbRegistered])) {
- if (MaxDimmPerCH == 3) {
- if (NBPtr->ChannelPtr->Dimms == 1) {
- if ((NBPtr->ChannelPtr->DimmDrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
- DramTermDyn = 1;
- }
- }
- }
- }
- MrsAddress |= (UINT16) DramTermDyn << 9;
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS3 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-STATIC
-MemTEMRS33 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=1,BA0=1
- NBPtr->SetBitField (NBPtr, BFMrsBank, 3);
-
- // program MrsAddress[1:0]=multi purpose register address location
- // (MPR Location):based on F2x[1,0]84[MprLoc]
- // program MrsAddress[2]=multi purpose register
- // (MPR):based on F2x[1,0]84[MprEn]
- NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This sets MRS value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-STATIC
-MemTMRS3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT32 MrsAddress;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=0,BA0=0
- NBPtr->SetBitField (NBPtr, BFMrsBank, 0);
-
- // program MrsAddress[1:0]=burst length and control method
- // (BL):based on F2x[1,0]84[BurstCtrl]
- MrsAddress = NBPtr->GetBitField (NBPtr, BFBurstCtrl);
-
- // program MrsAddress[3]=1 (BT):interleaved
- MrsAddress |= (UINT16) 1 << 3;
-
- // program MrsAddress[6:4,2]=read CAS latency
- // (CL):based on F2x[1,0]88[Tcl]
- // -- F2x88[3:0] to MrsAddress[6:4,2]=xxx0b --
- MrsAddress |= NBPtr->GetBitField (NBPtr, BFTcl) << 4;
-
- // program MrsAddress[11:9]=write recovery for auto-precharge
- // (WR):based on F2x[1,0]84[Twr]
- MrsAddress |= NBPtr->GetBitField (NBPtr, BFTwrDDR3) << 9;
-
- // program MrsAddress[12] (PPD):based on F2x[1,0]84[PChgPDModeSel]
- MrsAddress |= NBPtr->GetBitField (NBPtr, BFPchgPDModeSel) << 12;
-
- // program MrsAddress[8]=1 (DLL):DLL reset
- MrsAddress |= (UINT32) 1 << 8;
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This send all MR commands to a rank in sequence 2-3-1-0
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ChipSel - Target Chip Select
- */
-
-VOID
-MemTSendAllMRCmds3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
-
- // 13.Send EMRS(2)
- MemTEMRS23 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
- MemTEMRS33 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- // 15.Send EMRS(1).
- MemTEMRS13 (TechPtr, FALSE, (ChipSel >> 1));
- NBPtr->SendMrsCmd (NBPtr);
-
- // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
- MemTMRS3 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h
deleted file mode 100644
index aaa7b61716..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * @file
- *
- * mtsdi3.h
- *
- * Technology software DRAM init for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSDI3_H_
-#define _MTSDI3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-MemTEMRS13 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN BOOLEAN Wl,
- IN UINT8 TargetDIMM
- );
-
-VOID
-MemTEMRS23 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
deleted file mode 100644
index cfe30a96aa..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
+++ /dev/null
@@ -1,1089 +0,0 @@
-/**
- * @file
- *
- * mtspd3.c
- *
- * Technology SPD supporting functions for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mu.h"
-#include "mtspd3.h"
-#include "mftds.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_TECH_DDR3_MTSPD3_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemTCRCCheck3 (
- IN OUT UINT8 *SPDPtr
- );
-
-UINT8
-STATIC
-MemTSPDGetTCL3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-STATIC
-MemTCheckBankAddr3 (
- IN UINT8 Encode,
- OUT UINT8 *Index
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DRAM mode
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that the DRAM mode is set to DDR3
- */
-
-BOOLEAN
-MemTSetDramMode3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTDIMMPresence3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 *SpdBufferPtr = NULL;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- BOOLEAN SPDCtrl;
- UINT8 Devwidth;
- UINT8 MaxDimms;
- UINT8 Value8;
- UINT16 DimmMask;
-
- NBPtr = TechPtr->NBPtr;
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- printk(BIOS_DEBUG, " Dct %x ", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- printk(BIOS_DEBUG, "Channel %x\n", Channel);
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->DimmQrPresent = 0;
- //
- // Get the maximum number of DIMMs
- //
- MaxDimms = MAX_DIMMS_PER_CHANNEL;
- for (i = 0; i < MaxDimms; i++) {
- // Bitmask representing dimm #i.
- DimmMask = (UINT16)1 << i;
- //
- if (MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i)) {
- MCTPtr->DimmPresent |= DimmMask;
- //
- // Check for valid checksum value
- //
- AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
- if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) {
- ChannelPtr->ChDimmValid |= DimmMask;
- MCTPtr->DimmValid |= DimmMask;
- } else {
- // Current socket is set up to only support DDR3 dimms.
- IDS_ERROR_TRAP;
- }
- if (!MemTCRCCheck3 (SpdBufferPtr) && !SPDCtrl) {
- //
- // NV_SPDCHK_RESTRT is set to 0,
- // cannot ignore faulty SPD checksum
- //
- // Indicate checksum error
- ChannelPtr->DimmSpdCse |= DimmMask;
- PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
- //
- // Check module type information.
- //
- if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) {
- ChannelPtr->RegDimmPresent |= DimmMask;
- MCTPtr->RegDimmPresent |= DimmMask;
- if (!UserOptions.CfgMemoryRDimmCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_RDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- IDS_ERROR_TRAP;
- }
- }
- if ((SpdBufferPtr[SPD_DIMM_TYPE] == JED_UDIMM) && !UserOptions.CfgMemoryUDimmCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- IDS_ERROR_TRAP;
- }
- if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) {
- ChannelPtr->SODimmPresent |= DimmMask;
- if (!UserOptions.CfgMemorySODimmCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_SODIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- IDS_ERROR_TRAP;
- }
- }
- //
- // Check error correction type
- //
- if ((SpdBufferPtr[SPD_ECCBITS] & JED_ECC) != 0) {
- MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC
- }
- //
- // Get the Dimm width data
- //
- Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7;
- switch (Devwidth) {
- case 0:
- ChannelPtr->Dimmx4Present |= DimmMask;
- Devwidth = 4;
- break;
- case 1:
- ChannelPtr->Dimmx8Present |= DimmMask;
- Devwidth = 8;
- break;
- case 2:
- ChannelPtr->Dimmx16Present |= DimmMask;
- Devwidth = 16;
- break;
- default:
- IDS_ERROR_TRAP;
- }
- //
- // Check for 'analysis probe installed'
- // if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK)
- //
- // Determine the geometry of the DIMM module
- // if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT)
- //
- // specify the number of ranks
- //
- Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
- if (Value8 > 2) {
- if (!UserOptions.CfgMemoryQuadRankCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_QRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- }
- //
- // Mark this Dimm as Quad Rank
- //
- ChannelPtr->DimmQrPresent |= DimmMask;
- Value8 = 2;
- } else if (Value8 == 2) {
- ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms
- } else {
- ChannelPtr->DimmSRPresent |= DimmMask; // Single rank dimms
- }
- //
- // Calculate bus loading per Channel
- if (Devwidth == 16) {
- Devwidth = 4;
- } else if (Devwidth == 4) {
- Devwidth = 16;
- }
- //
- // double Addr bus load value for dual rank DIMMs
- //
- if (Value8 == 2) {
- Devwidth = Devwidth << 1;
- }
- //
- ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
- ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
- if ((i < 2) || ((ChannelPtr->DimmQrPresent & DimmMask) == 0)) {
- ChannelPtr->Dimms++;
- }
- //
- // Check address mirror support for Unbuffered Dimms only
- //
- if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) {
- if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
- ChannelPtr->DimmMirrorPresent |= DimmMask;
- }
- }
- //
- // Get byte62: Reference Raw Card information
- //
- ChannelPtr->RefRawCard[i] = SpdBufferPtr[SPD_RAWCARD] & 0x1F;
- //
- // Get control word values for RC3, RC4 and RC5
- //
- ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4;
- ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F;
- ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4;
- //
- // Temporarily store info. of SPD byte 63 into CtrlWrd02(s),
- // and they will be used late to calculate real RC2 and RC8 value
- //
- ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03;
- //
- } // if DIMM present
- } // Dimm loop
-
- if (Channel == 0) {
- DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
- DCTPtr->Timings.DimmMirrorPresent = ChannelPtr->DimmMirrorPresent;
- DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
- DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
- DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
- DCTPtr->Timings.DimmSRPresent = ChannelPtr->DimmSRPresent;
- DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
- DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
- DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
- }
- if ((Channel != 1) || (Dct != 1)) {
- MCTPtr->DimmPresent <<= 8;
- MCTPtr->DimmValid <<= 8;
- MCTPtr->RegDimmPresent <<= 8;
- MCTPtr->DimmEccPresent <<= 8;
- MCTPtr->DimmParPresent <<= 8;
- }
- printk(BIOS_DEBUG, " RegDimmPresent: %x\n", ChannelPtr->RegDimmPresent);
- printk(BIOS_DEBUG, " SODimmPresent: %x\n", ChannelPtr->SODimmPresent);
- printk(BIOS_DEBUG, " ChDimmValid: %x\n", ChannelPtr->ChDimmValid);
- printk(BIOS_DEBUG, " DimmPlPresent: %x\n", ChannelPtr->DimmPlPresent);
- printk(BIOS_DEBUG, " DimmQrPresent: %x\n", ChannelPtr->DimmQrPresent);
- printk(BIOS_DEBUG, " DimmDrPresent: %x\n", ChannelPtr->DimmDrPresent);
- printk(BIOS_DEBUG, " DimmSRPresent: %x\n", ChannelPtr->DimmSRPresent);
- printk(BIOS_DEBUG, " Dimmx4Present: %x\n", ChannelPtr->Dimmx4Present);
- printk(BIOS_DEBUG, " DimmX8Present: %x\n", ChannelPtr->Dimmx8Present);
- printk(BIOS_DEBUG, " DimmX16Present: %x\n", ChannelPtr->Dimmx16Present);
- printk(BIOS_DEBUG, " DimmMirrorPresent: %x\n", ChannelPtr->DimmMirrorPresent);
- } // Channel loop
- } // DCT loop
-
- // If we have DIMMs, some further general characteristics checking
- if (MCTPtr->DimmValid != 0) {
- // If there are registered dimms, all the dimms must be registered
- if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
- // All dimms registered
- MCTPtr->Status[SbRegistered] = TRUE;
- MCTPtr->Status[SbParDimms] = TRUE; // All DDR3 RDIMMs are parity capable
- TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgsRDdr3; // Change the function pointer for DQS ECC timing
- } else if (MCTPtr->RegDimmPresent != 0) {
- // We have an illegal DIMM mismatch
- PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- }
-
- // check the ECC capability of the DIMMs
- if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable
- }
- } else {
- }
-
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->SwitchChannel (NBPtr, 0);
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finds the maximum frequency that each channel is capable to run at.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDGetTargetSpeed3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr = NULL;
- UINT8 Dimm;
- UINT8 Dct;
- UINT8 Channel;
- UINT16 MTB16x;
- UINT16 TCKmin16x;
- UINT16 Value16;
- MEM_NB_BLOCK *NBPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- TCKmin16x = 0;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
-
- // Determine tCKmin(all) which is the largest tCKmin
- // value for all modules on the memory Channel (SPD byte 12).
- //
- MTB16x = ((UINT16)SpdBufferPtr[SPD_DIVIDENT] << 4) / SpdBufferPtr[SPD_DIVISOR];
- Value16 = SpdBufferPtr[SPD_TCK] * MTB16x;
- if (TCKmin16x < Value16) {
- TCKmin16x = Value16;
- }
- }
- }
- }
- if (TCKmin16x <= 17) {
- DCTPtr->Timings.TargetSpeed = DDR1866_FREQUENCY;
- } else if (TCKmin16x <= 20) {
- DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY;
- } else if (TCKmin16x <= 24) {
- DCTPtr->Timings.TargetSpeed = DDR1333_FREQUENCY;
- } else if (TCKmin16x <= 30) {
- DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY;
- } else if (TCKmin16x <= 40) {
- DCTPtr->Timings.TargetSpeed = DDR800_FREQUENCY;
- } else {
- DCTPtr->Timings.TargetSpeed = DDR667_FREQUENCY;
- }
- }
-
- // Ensure the target speed can be applied to all channels of the current node
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Set the start-up frequency
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.Speed = TechPtr->NBPtr->StartupSpeed;
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
- * DIMM on Channel B), the overall DIMM population, and determine the width mode:
- * 64-bit, 64-bit muxed, 128-bit.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDCalcWidth3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferAPtr = NULL;
- UINT8 *SpdBufferBPtr = NULL;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 i;
- UINT16 DimmMask;
- UINT8 UngangMode;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- UngangMode = UserOptions.CfgMemoryModeUnganged;
- // Does not support ganged mode for DDR3 dimms
- ASSERT (UngangMode);
- IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
-
- // Check symmetry of channel A and channel B dimms for 128-bit mode
- // capability.
- //
- AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
- i = 0;
- if (!UngangMode) {
- if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
- for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
- DimmMask = (UINT16)1 << i;
- if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
- NBPtr->SwitchDCT (NBPtr, 0);
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferAPtr, i);
- NBPtr->SwitchDCT (NBPtr, 1);
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferBPtr, i);
- // compare rows and columns
- if ((SpdBufferAPtr[SPD_ROW_SZ]&0x3F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x3F)) {
- break;
- }
- if ((SpdBufferAPtr[SPD_DENSITY]&0x0F) != (SpdBufferBPtr[SPD_DENSITY]&0x0F)) {
- break;
- }
- // compare ranks and devwidth
- if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
- break;
- }
- }
- }
- }
- if (i < MAX_DIMMS_PER_CHANNEL) {
- PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ALERT, MCTPtr);
- } else {
- NBPtr->Ganged = TRUE;
- MCTPtr->GangedMode = TRUE;
- MCTPtr->Status[Sb128bitmode] = TRUE;
- NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
- }
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Initialize DCT Timing registers as per DIMM SPD.
- * For primary timing (T, CL) use best case T value.
- * For secondary timing params., use most aggressive settings
- * of slowest DIMM.
- *
- * Note:
- * There are three components to determining "maximum frequency": SPD component,
- * Bus load component, and "Preset" max frequency component.
- * The SPD component is a function of the min cycle time specified by each DIMM,
- * and the interaction of cycle times from all DIMMs in conjunction with CAS
- * latency. The SPD component only applies when user timing mode is 'Auto'.
- *
- * The Bus load component is a limiting factor determined by electrical
- * characteristics on the bus as a result of varying number of device loads. The
- * Bus load component is specific to each platform but may also be a function of
- * other factors. The bus load component only applies when user timing mode is
- * ' Auto'.
- *
- * The Preset component is subdivided into three items and is the minimum of
- * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
- * memclock mode is 'Limit', OEM build specification of the maximum frequency.
- * The Preset component only applies when user timing mode is 'Auto'.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTAutoCycTiming3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT8 SpdIndexes[] = {
- SPD_TRCD,
- SPD_TRP,
- SPD_TRTP,
- SPD_TRAS,
- SPD_TRC,
- SPD_TWR,
- SPD_TRRD,
- SPD_TWTR,
- SPD_TFAW
- };
-
- UINT8 *SpdBufferPtr = NULL;
- UINT16 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
- UINT8 MiniMaxTrfc[4];
-
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 DimmMask;
- UINT16 Value16;
- UINT16 MTB16x;
- UINT16 TCK16x;
- UINT8 i;
- UINT8 j;
- UINT8 Value8;
- UINT8 *StatTmgPtr;
- UINT16 *StatDimmTmgPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- // initialize mini-max arrays
- for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
- MiniMaxTmg[j] = 0;
- }
- for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
- MiniMaxTrfc[j] = 0;
- }
-
- // ======================================================================
- // Get primary timing (CAS Latency and Cycle Time)
- // ======================================================================
- // Get OEM specific load variant max
- //
-
- //======================================================================
- // Gather all DIMM mini-max values for cycle timing data
- //======================================================================
- //
- DimmMask = 1;
- for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
- if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i);
- MTB16x = ((UINT16)SpdBufferPtr[SPD_DIVIDENT] << 4) / SpdBufferPtr[SPD_DIVISOR];
-
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value16 = (UINT16)SpdBufferPtr[SpdIndexes[j]];
- if (SpdIndexes[j] == SPD_TRC) {
- Value16 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRC] & 0xF0) << 4;
- } else if (SpdIndexes[j] == SPD_TRAS) {
- Value16 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRAS] & 0x0F) << 8;
- } else if (SpdIndexes[j] == SPD_TFAW) {
- Value16 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TFAW] & 0x0F) << 8;
- }
- Value16 = Value16 * MTB16x;
- if (MiniMaxTmg[j] < Value16) {
- MiniMaxTmg[j] = Value16;
- }
- }
-
- // get Trfc0 - Trfc3 values
- Value8 = SpdBufferPtr[SPD_DENSITY] & 0x0F;
- if (MiniMaxTrfc[i] < Value8) {
- MiniMaxTrfc[i] = Value8;
- }
- }
- DimmMask <<= 1;
- }
-
- // ======================================================================
- // Convert DRAM CycleTiming values and store into DCT structure
- // ======================================================================
- //
- TCK16x = (16000 + 16) / DCTPtr->Timings.Speed; // Offset of 16 is used to round to the nearest integer
-
- // Notes:
- // 1. All secondary time values given in SPDs are in binary with UINTs of ns.
- // 2. All time values are scaled by 16, in order to have least count of 0.125 ns
- // (more accuracy).
- // 3. Internally to this SW, cycle time, TCK16x, is scaled by 16 to match time values
- //
- StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
- StatTmgPtr = &DCTPtr->Timings.Trcd;
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value16 = MiniMaxTmg[j];
-
- MiniMaxTmg[j] = (MiniMaxTmg[j] + TCK16x - 1) / TCK16x;
-
- StatDimmTmgPtr[j] = Value16;
- StatTmgPtr[j] = (UINT8)MiniMaxTmg[j];
- }
- DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
- DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
- DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
- DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
-
- DCTPtr->Timings.CasL = MemTSPDGetTCL3 (TechPtr);
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- NBPtr->ProgramCycTimings (NBPtr);
-
- MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the bank addressing, program Mask values and build a chip-select population map.
- * This routine programs PCI 0:24N:2x80 config register.
- * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDSetBanks3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr = NULL;
- UINT8 i;
- UINT8 ChipSel;
- UINT8 DimmID;
- UINT8 Value8;
- UINT8 Rows;
- UINT8 Cols;
- UINT8 Ranks;
- UINT8 Banks;
- UINT32 BankAddrReg;
- UINT32 CsMask;
- UINT16 CSSpdCSE;
- UINT16 CSExclude;
- UINT16 DimmQRDR;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- BankAddrReg = 0;
- CSSpdCSE = 0;
- CSExclude = 0;
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- DimmID = ChipSel >> 1;
-
- DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
- if ((DCTPtr->Timings.DimmSpdCse & ((UINT16) 1 << DimmID)) != 0) {
- CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
- }
- if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
- CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
- }
-
- if ((DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, DimmID);
-
- // Get the basic data
- Rows = (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7;
- Cols = SpdBufferPtr[SPD_COL_SZ] & 0x7;
- Banks = (SpdBufferPtr[SPD_L_BANKS] >> 4) & 0x7;
- Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
-
- //
- // Configure the bank encoding
- // Use a 6-bit key into a lookup table.
- // Key (index) = RRRBCC, where CC is the number of Columns minus 9,
- // RRR is the number of Rows minus 12, and B is the number of banks
- // minus 3.
- //
- Value8 = Cols;
- Value8 |= (Banks == 1) ? 4 : 0;
- Value8 |= Rows << 3;
-
- if (MemTCheckBankAddr3 (Value8, &i)) {
- BankAddrReg |= ((UINT32)i << (ChipSel << 1));
-
- // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
- // or 2pow(rows+cols+banks-5)-1
- //
- Value8 = (Rows + 12) + (Cols + 9) + (Banks + 3) + 3 - 8;
- if (MCTPtr->Status[Sb128bitmode]) {
- Value8++;
- }
- CsMask = ((UINT32)1 << Value8) - 1;
- DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
-
- if (Ranks >= 2) {
- DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
- }
-
- // Update the DRAM CS Mask for this chipselect
- NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & 0x1FF83FE0));
- } else {
- // Dimm is not supported, as no address mapping is found.
- DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
- DCTPtr->Timings.CsTestFail |= (UINT16)1 << ChipSel;
- if (Ranks >= 2) {
- DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
- DCTPtr->Timings.CsTestFail |= (UINT16)1 << (ChipSel + 1);
- }
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_ADDRESS_MAPPING, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, DimmID, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
- }
- }
- // For ranks that need to be excluded, the loading of this rank should be considered
- // in timing, so need to set CsPresent before setting CsTestFail
- if ((CSSpdCSE != 0) || (CSExclude != 0)) {
- NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader);
- }
-
- // If there are no chip selects, we have an error situation.
- if (DCTPtr->Timings.CsPresent == 0) {
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the low bit that will be swapped to enable CS interleaving
- *
- * @param[in] BankEnc - AddrMap Bank encoding from F2x80
- * @param[in] *LowBit - pointer to low bit
- * @param[in] *HiBit - pointer hight bit
- *
- */
-
-VOID
-MemTGetCSIntLvAddr3 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- )
-{
- CONST UINT8 ArrCodesLo[] = {0, 8, 8, 0, 0, 8, 9, 8, 9, 9, 8, 9};
- CONST UINT8 ArrCodesHi[] = {0, 20, 21, 0, 0, 22, 22, 23, 23, 24, 24, 25};
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
- // return ArrCodes[BankEnc];
- *LowBit = ArrCodesLo[BankEnc];
- *HiBit = ArrCodesHi[BankEnc];
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if the checksum is correct
- *
- * @param[in] *SPDPtr - Pointer to SPD data
- *
- * @return TRUE - CRC check passes
- * @return FALSE - CRC check fails
- */
-
-BOOLEAN
-STATIC
-MemTCRCCheck3 (
- IN OUT UINT8 *SPDPtr
- )
-{
- UINT16 Crc;
- INT16 i;
- INT16 j;
- INT16 Count;
-
- if (SPDPtr[SPD_TYPE] == JED_DDR3SDRAM) {
- Count = (SPDPtr[SPD_BYTE_USED] & 0x80) ? 117 : 126;
- Crc = 0;
- for (j = 0; j < Count; j++) {
- Crc = Crc ^ ((UINT16)SPDPtr[j] << 8);
- for (i = 0; i < 8; i++) {
- if (Crc & 0x8000) {
- Crc = (Crc << 1) ^ 0x1021;
- } else {
- Crc = (Crc << 1);
- }
- }
- }
- if (*(UINT16 *) (SPDPtr + 126) == Crc) {
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return CAS Latency
- */
-
-UINT8
-STATIC
-MemTSPDGetTCL3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr = NULL;
- UINT8 CLdesired;
- UINT8 CLactual;
- UINT8 Dimm;
- UINT8 Channel;
- UINT16 CASLat;
- UINT16 MTB16x;
- UINT16 TAAmin16x;
- UINT16 TCKproposed16x;
- UINT16 Value16;
- UINT16 Mask16;
- BOOLEAN CltFail;
- MEM_NB_BLOCK *NBPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- CASLat = 0xFFFF;
- TAAmin16x = 0;
- CltFail = FALSE;
-
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
-
- // Step 1: Determine the common set of supported CAS Latency
- // values for all modules on the memory Channel using the CAS
- // Latencies Supported in SPD bytes 14 and 15.
- //
- CASLat &= ((UINT16)SpdBufferPtr[SPD_CASHI] << 8) | SpdBufferPtr[SPD_CASLO];
-
- // Step 2: Determine tAAmin(all) which is the largest tAAmin
- // value for all modules on the memory Channel (SPD byte 16).
- //
- MTB16x = ((UINT16)SpdBufferPtr[SPD_DIVIDENT] << 4) / SpdBufferPtr[SPD_DIVISOR];
- Value16 = SpdBufferPtr[SPD_TAA] * MTB16x;
- if (TAAmin16x < Value16) {
- TAAmin16x = Value16;
- }
-
- // Step 3: Determine tCKmin(all) which is the largest tCKmin
- // value for all modules on the memory Channel (SPD byte 12).
- // * This step has been done in SPDGetTargetSpeed
- }
- }
- }
-
- TCKproposed16x = (16000 + 16) / DCTPtr->Timings.Speed; // Offset of 16 is used to round to the nearest integer
-
- // Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax,
- // determine the desired CAS Latency. If tCKproposed is not a standard JEDEC
- // value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the
- // next lower standard tCK value for calculating CLdesired.
- // CLdesired = ceiling ( tAAmin(all) / tCKproposed )
- // where tAAmin is defined in Byte 16. The ceiling function requires that the
- // quotient be rounded up always.
- //
- CLdesired = (UINT8) ((TAAmin16x + TCKproposed16x - 1) / TCKproposed16x);
-
- // Step 5: Choose an actual CAS Latency (CLactual) that is greater than or equal
- // to CLdesired and is supported by all modules on the memory Channel as
- // determined in step 1. If no such value exists, choose a higher tCKproposed
- // value and repeat steps 4 and 5 until a solution is found.
- //
- CLactual = 4;
- for (Mask16 = 1; Mask16 < 0x8000; Mask16 <<= 1) {
- if (CASLat & Mask16) {
- if (CLdesired <= CLactual) {
- break;
- }
- }
- CLactual++;
- }
- if (Mask16 == 0x8000) {
- CltFail = TRUE;
- }
-
- // Step 6: Once the calculation of CLactual is completed, the BIOS must also
- // verify that this CAS Latency value does not exceed tAAmax, which is 20 ns
- // for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If
- // not, choose a lower CL value and repeat steps 5 and 6 until a solution is found.
- //
- if ((TCKproposed16x * CLactual) > 320) {
- CltFail = TRUE;
- }
-
- if (!CltFail) {
- DCTPtr->Timings.CasL = CLactual;
- } else {
- // Fail to find supported Tcl, use 6 clocks since it is required for all DDR3 speed bin.
- DCTPtr->Timings.CasL = 6;
- }
-
- return DCTPtr->Timings.CasL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the encoded value of bank address.
- *
- * @param[in] Encode - RRRBCC, where CC is the number of Columns minus 9,
- * RRR is the number of Rows minus 12, and B is the number of banks
- * minus 3.
- * @param[out] *Index - index in bank address table
- * @return TRUE - encoded value is found.
- * FALSE - encoded value is not found.
- */
-
-BOOLEAN
-STATIC
-MemTCheckBankAddr3 (
- IN UINT8 Encode,
- OUT UINT8 *Index
- )
-{
- UINT8 i;
- CONST UINT8 TabBankAddr[] = {
- 0x3F, 0x01, 0x09, 0x3F, 0x3F, 0x11,
- 0x0A, 0x19, 0x12, 0x1A, 0x21, 0x22
- };
-
- for (i = 0; i < GET_SIZE_OF (TabBankAddr); i++) {
- if (Encode == TabBankAddr[i]) {
- *Index = i;
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns a pointer to the SPD Buffer of a specific dimm on
- * the current channel.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
- * @param[in] Dimm - Dimm number
- *
- *
- * @return BOOLEAN - Value of DimmPresent
- * TRUE = Dimm is present, pointer is valid
- * FALSE = Dimm is not present, pointer has not been modified.
- */
-
-BOOLEAN
-MemTGetDimmSpdBuffer3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- )
-{
- CH_DEF_STRUCT *ChannelPtr;
- SPD_DEF_STRUCT *SPDPtr;
- BOOLEAN DimmPresent;
-
- DimmPresent = FALSE;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
- SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
-
-
- if (SPDPtr != NULL) {
- DimmPresent = SPDPtr->DimmPresent;
- if (DimmPresent) {
- *SpdBuffer = SPDPtr->Data;
- }
- }
- return DimmPresent;
-}
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h
deleted file mode 100644
index b63fd760f4..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * @file
- *
- * mtspd3.h
- *
- * Technology SPD support for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSPD3_H_
-#define _MTSPD3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*===============================================================================
- * Jedec DDR III
- *===============================================================================
- */
-#define SPD_BYTE_USED 0
-#define SPD_TYPE 2 /* SPD byte read location */
-#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
-#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
-#define JED_DDR3SDRAM 0xB /* Jedec defined bit field */
-
-#define SPD_DIMM_TYPE 3
-#define SPD_ATTRIB 21
-#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
-#define JED_RDIMM 1
-#define JED_MINIRDIMM 5
-#define JED_UDIMM 2
-#define JED_SODIMM 3
-
-#define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */
-#define SPD_DENSITY 4 /* bit 3:0 */
-#define SPD_ROW_SZ 5 /* bit 5:3 */
-#define SPD_COL_SZ 5 /* bit 2:0 */
-#define SPD_RANKS 7 /* bit 5:3 */
-#define SPD_DEV_WIDTH 7 /* bit 2:0 */
-#define SPD_ECCBITS 8 /* bit 4:3 */
-#define JED_ECC 8
-#define SPD_RAWCARD 62 /* bit 2:0 */
-#define SPD_ADDRMAP 63 /* bit 0 */
-
-#define SPD_CTLWRD03 70 /* bit 7:4 */
-#define SPD_CTLWRD04 71 /* bit 3:0 */
-#define SPD_CTLWRD05 71 /* bit 7:4 */
-
-#define SPD_DIVIDENT 10
-#define SPD_DIVISOR 11
-
-#define SPD_TCK 12
-#define SPD_CASLO 14
-#define SPD_CASHI 15
-#define SPD_TAA 16
-
-#define SPD_TRP 20
-#define SPD_TRRD 19
-#define SPD_TRCD 18
-#define SPD_TRAS 22
-#define SPD_TWR 17
-#define SPD_TWTR 26
-#define SPD_TRTP 27
-#define SPD_TRC 23
-#define SPD_UPPER_TRC 21 /* bit 7:4 */
-#define SPD_UPPER_TRAS 21 /* bit 3:0 */
-#define SPD_TFAW 29
-#define SPD_UPPER_TFAW 28 /* bit 3:0 */
-
-/*-----------------------------
- * Jedec DDR II related equates
- *-----------------------------
- */
-
-#define CL_DEF 4 /* Default value for failsafe operation. 4=CL 6.0 T */
-#define T_DEF 4 /* Default value for failsafe operation. 4=2.5ns (cycle time) */
-
-#define BIAS_TRTP_T 4
-#define BIAS_TRCD_T 5
-#define BIAS_TRAS_T 15
-#define BIAS_TRC_T 11
-#define BIAS_TRRD_T 4
-#define BIAS_TWR_T 4
-#define BIAS_TRP_T 5
-#define BIAS_TWTR_T 4
-#define BIAS_TFAW_T 14
-
-#define MIN_TRTP_T 4
-#define MAX_TRTP_T 7
-#define MIN_TRCD_T 5
-#define MAX_TRCD_T 12
-#define MIN_TRAS_T 15
-#define MAX_TRAS_T 30
-#define MIN_TRC_T 11
-#define MAX_TRC_T 42
-#define MIN_TRRD_T 4
-#define MAX_TRRD_T 7
-#define MIN_TWR_T 5
-#define MAX_TWR_T 12
-#define MIN_TRP_T 5
-#define MAX_TRP_T 12
-#define MIN_TWTR_T 4
-#define MAX_TWTR_T 7
-#define MIN_TFAW_T 16
-#define MAX_TFAW_T 32
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-#endif /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c
deleted file mode 100644
index 8cca4f7262..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/**
- * @file
- *
- * mttecc3.c
- *
- * Technology ECC byte support for registered DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 12509 $ @e \$Date: 2009-04-20 21:38:29 -0500 (Mon, 20 Apr 2009) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DQS ECC timings for registered DDR3
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTSetDQSEccTmgsRDdr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 Dimm;
- UINT8 i;
- UINT8 *WrDqsDly;
- UINT16 *RcvEnDly;
- UINT8 *RdDqsDly;
- UINT8 *WrDatDly;
- UINT8 EccByte;
- INT16 TempValue;
-
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- EccByte = TechPtr->MaxByteLanes ();
- NBPtr = TechPtr->NBPtr;
-
- if (NBPtr->MCTPtr->NodeMemSize) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) {
- i = Dimm * TechPtr->DlyTableWidth ();
- WrDqsDly = &ChannelPtr->WrDqsDlys[i];
- RcvEnDly = &ChannelPtr->RcvEnDlys[i];
- RdDqsDly = &ChannelPtr->RdDqsDlys[i];
- WrDatDly = &ChannelPtr->WrDatDlys[i];
- // Receiver DQS Enable:
- // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 -
- // [write DQS for bytelane 3 - write DQS for ECC]
-
- TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]);
- if (TempValue < 0) {
- TempValue = 0;
- }
- RcvEnDly[EccByte] = (UINT16) TempValue;
-
- // Read DQS:
- // Read DQS for ECC bytelane = read DQS of byte lane 3
- //
- RdDqsDly[EccByte] = RdDqsDly[3];
-
- // Write Data:
- // Write Data for ECC bytelane = Write DQS for ECC +
- // [write data for bytelane 3 - Write DQS for bytelane 3]
- TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3]));
- if (TempValue < 0) {
- TempValue = 0;
- }
- WrDatDly[EccByte] = (UINT8) TempValue;
-
- NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]);
- NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]);
- NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]);
- }
- }
- }
- }
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-} \ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
deleted file mode 100644
index 660f227f14..0000000000
--- a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
+++ /dev/null
@@ -1,603 +0,0 @@
-/**
- * @file
- *
- * mttwl3.c
- *
- * Technology Phy assisted write levelization for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtsdi3.h"
-#include "merrhdl.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_TECH_DDR3_MTTWL3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-STATIC
-MemTWriteLevelizationHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- );
-
-VOID
-STATIC
-MemTWLPerDimmHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- );
-
-VOID
-STATIC
-MemTPrepareDIMMs3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 TargetDIMM,
- IN BOOLEAN Wl
- );
-
-VOID
-STATIC
-MemTProcConfig3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- );
-
-VOID
-STATIC
-MemTBeginWLTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes first pass of Phy assisted write levelization
- * for a specific node (DDR800).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTWriteLevelizationHw3Pass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return MemTWriteLevelizationHw3 (TechPtr, 1);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes second pass of Phy assisted write levelization
- * for a specific node (DDR1066 and above).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTWriteLevelizationHw3Pass2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- // If current speed is higher than start-up speed, do second pass of WL
- if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) {
- return MemTWriteLevelizationHw3 (TechPtr, 2);
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function prepares for Phy assisted training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTPreparePhyAssistedTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1.
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 1);
- // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b.
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 0);
- return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function revert to normal settings when exiting from Phy assisted training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTExitPhyAssistedTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- // 13.Program F2x[1, 0]8C[DisAutoRefresh] = 0.
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 0);
- // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration.
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 2);
- return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executed hardware based write levelization for a specific die
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
- *
- * @pre Auto refresh and ZQCL must be disabled
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-STATIC
-MemTWriteLevelizationHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- )
-{
- MEM_NB_BLOCK *NBPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 Dct;
- UINT8 Dimm;
-
- NBPtr = TechPtr->NBPtr;
-
- IDS_HDT_CONSOLE ("!\nStart write leveling\n");
- AGESA_TESTPOINT (TpProcMemWriteLevelizationTraining, &(NBPtr->MemPtr->StdHeader));
- // Begin DQS Write timing training
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
- DCTPtr = NBPtr->DCTPtr;
-
- //training for each Dimm
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) {
-
- IDS_HDT_CONSOLE ("!\t\tCS %d\n", Dimm << 1);
- MemTWLPerDimmHw3 (TechPtr, Dimm, Pass);
- }
- }
- }
- IDS_HDT_CONSOLE ("End write leveling\n\n");
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes per DIMM write levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - DIMM to be trained
- * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
- *
- */
-
-VOID
-STATIC
-MemTWLPerDimmHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL);
-
- // 1. Specify the target Dimm that is to be trained by programming
- // F2x[1, 0]9C_x08[TrDimmSel].
- NBPtr->SetBitField (NBPtr, BFTrDimmSel, Dimm);
-
- // 2. Prepare the DIMMs for write levelization using DDR3-defined
- // MR commands.
- MemTPrepareDIMMs3 (TechPtr, Dimm, TRUE);
-
- // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to
- // satisfy DDR3-defined internal DRAM timing.
- MemUWait10ns (10, MemPtr);
-
- // 4. Configure the processor's DDR phy for write levelization training:
- MemTProcConfig3 (TechPtr, Dimm, Pass);
-
- // 5. Begin write levelization training
- MemTBeginWLTrain3 (TechPtr, Dimm);
-
- // 7. Program the target Dimm back to normal operation
- MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function prepares the DIMMS for Write Levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] TargetDIMM - DIMM to be trained
- * @param[in] Wl - Indicates if WL mode should be enabled
- *
- */
-
-VOID
-STATIC
-MemTPrepareDIMMs3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 TargetDIMM,
- IN BOOLEAN Wl
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT8 ChipSel;
-
- NBPtr = TechPtr->NBPtr;
-
- AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader));
- ASSERT (TargetDIMM < MAX_DIMMS_PER_CHANNEL);
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
- if (Wl) {
- // Program WrLvOdt
- NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[ChipSel >> 1]);
- }
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
- // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
- MemTEMRS13 (TechPtr, Wl, TargetDIMM);
- // Send command
- NBPtr->SendMrsCmd (NBPtr);
- // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
- MemTEMRS23 (TechPtr);
- // Send command
- NBPtr->SendMrsCmd (NBPtr);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs seed values for Write Levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - DIMM to be trained
- * @param[in] Pass - Pass for WL training (1 - 400Mhz or 2 - >400Mhz)
- *
- */
-
-VOID
-STATIC
-MemTProcConfig3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- )
-{
- DIE_STRUCT *MCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 WrDqsDly;
- // Memclk Delay incurred by register.
- UINT8 MemClkRegDly;
- UINT8 ByteLane;
- UINT8 DefaultSeed;
- UINT8 CurrentSeed;
- UINT8 *Seed;
- UINT8 RCW2;
- UINT16 Speed;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- AGESA_TESTPOINT (TpProcMemWlConfigDimms, &(NBPtr->MemPtr->StdHeader));
- RCW2 = ChannelPtr->CtrlWrd02[Dimm];
- Speed = TechPtr->NBPtr->DCTPtr->Timings.Speed;
-
- IDS_HDT_CONSOLE ("\n\t\t\tSeeds: ");
- // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set
- // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz,
- // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency,
- // use an initial total delay value.
- if (Pass == 1) {
- // Get the default value of seed
- DefaultSeed = 0x1A;
- if (MCTPtr->Status[SbRegistered]) {
- DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x41 : 0x51;
- }
-
- if (Speed == DDR667_FREQUENCY) {
- DefaultSeed = (UINT8) ((DefaultSeed * 333 + 399) / 400); //round up
- }
- ASSERT (Speed >= DDR667_FREQUENCY);
-
- // Get platform override seed
- Seed = (UINT8 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID);
-
- for (ByteLane = 0; ByteLane < 9; ByteLane++) {
- // This includes ECC as byte 8
- CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed);
- NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed);
- ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = CurrentSeed;
- IDS_HDT_CONSOLE ("%02x ", CurrentSeed);
- }
- } else {
- //10.Multiply the previously saved delay values in Pass 1, step #5 by (target frequency)/400 to find
- //the gross and fine delay initialization values at the target frequency. Use these values as the initial
- //seed values when executing Pass 2, step #4.
- for (ByteLane = 0; ByteLane < 9; ByteLane++) {
- // This includes ECC as byte 8
- WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane];
- //
- // For Registered Dimms
- //
- if (MCTPtr->Status[SbRegistered]) {
- MemClkRegDly = ((RCW2 & BIT0) == 0) ? 0x20 : 0x30;
- WrDqsDly = (UINT16) (MemClkRegDly + ((((UINT32) WrDqsDly - MemClkRegDly) * Speed) / TechPtr->PrevSpeed));
- } else {
- //
- // Unbuffered Dimms
- //
- WrDqsDly = (UINT16) (((UINT32) WrDqsDly * Speed) / TechPtr->PrevSpeed);
- }
-
- ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = (UINT8) WrDqsDly;
-
- if (NBPtr->IsSupported[WLSeedAdjust]) {
- // Adjust seed to avoid overflowing PRE for the case SeedGross >= 3
- if (WrDqsDly >= 0x60) {
- if ((WrDqsDly & 0x20) != 0) {
- // If (SeedGross is odd) then SeedPreGross = 1
- WrDqsDly = (WrDqsDly & 0x1F) | 0x20;
- } else {
- // If (SeedGross is even) then SeedPreGross = 2
- WrDqsDly = (WrDqsDly & 0x1F) | 0x40;
- }
- }
- }
-
- NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDly);
- IDS_HDT_CONSOLE ("%02x ", WrDqsDly);
- }
- }
- IDS_HDT_CONSOLE ("\n");
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function begins WL training for a specific DIMM
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - DIMM to be trained
- *
- */
-
-VOID
-STATIC
-MemTBeginWLTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT8 ByteLane;
- UINT8 Seed;
- UINT8 Delay;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
- // Assert ODT pins for write leveling
- NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1);
-
- // Wait 10 MEMCLKs to allow for ODT signal settling.
- MemUWait10ns (3, MemPtr);
-
- IDS_HDT_CONSOLE ("\t\t\tWrtLvTrEn = 1\n");
- // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1.
- NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1);
-
- // Wait 200 MEMCLKs. If executing pass 2, wait 32 MEMCLKs.
- MemUWait10ns (50, MemPtr);
-
- // Program F2x[1, 0]9C_x08[WrtLlTrEn]=0.
- NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0);
-
- // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings
- // for the target Dimm and save these values.
- IDS_HDT_CONSOLE ("\t\t\t PRE: ");
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) {
- // This includes ECC as byte 8
- Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane];
- Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
-// IDS_HDT_CONSOLE ("%v1%02x ", Delay);
- IDS_HDT_CONSOLE ("%02x ", Delay);
-
- if ((Delay > (Seed + 0x20)) || (Seed > (Delay + 0x20))) {
- //
- // If PRE comes back with more than Seed +/- 0x20, then this is an
- // unexpected condition. Log the condition.
- //
- PutEventLog (AGESA_ERROR, MEM_ERROR_WL_PRE_OUT_OF_RANGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ((Seed << 8) + Delay), &NBPtr->MemPtr->StdHeader);
- }
- if ((NBPtr->IsSupported[WLSeedAdjust]) && (Seed >= 0x60)) {
- // Recover WrDqsGrossDly:
- // WrDqsGrossDly = SeedGross + PhRecGrossDlyByte - SeedPreGross
- if ((Seed & 0x20) != 0) {
- // If (SeedGross is odd) then SeedPreGross = 1
- Delay += (Seed & 0xE0) - 0x20;
- } else {
- // If (SeedGross is even) then SeedPreGross = 2
- Delay += (Seed & 0xE0) - 0x40;
- }
- } else if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) {
- IDS_OPTION_HOOK (IDS_CHECK_NEGATIVE_WL, &Delay, &(TechPtr->NBPtr->MemPtr->StdHeader));
- // If seed has gross delay of 0 and PRE has gross delay of 3,
- // then round the total delay of TxDqs to 0.
- Delay = 0;
- }
- NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay);
- NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] = Delay;
-// IDS_HDT_CONSOLE ("%v2%02x ", Delay);
- }
-#if 0
- IDS_HDT_CONSOLE ("%v0");
- IDS_HDT_CONSOLE ("\t\t\tPRE: %vh1\n");
- IDS_HDT_CONSOLE ("\t\t\tWrDqs: %vh2\n\n");
-#endif
- IDS_HDT_CONSOLE ("\n\t\t\tWrDqs: ");
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- IDS_HDT_CONSOLE ("%02x ", NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]);
- }
- IDS_HDT_CONSOLE("\n\n");
-
- // Disable write leveling ODT pins
- NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0);
-
- // Wait 10 MEMCLKs to allow for ODT signal settling.
- MemUWait10ns (3, MemPtr);
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs register after Phy assisted training is finish.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTExitPhyAssistedTrainingClient3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFRxPtrInitReq, 1);
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisDllShutdownSR, 1);
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFEnterSelfRef, 1);
- TechPtr->NBPtr->PollBitField (TechPtr->NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDbeGskMemClkAlignMode, 2);
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFExitSelfRef, 1);
- TechPtr->NBPtr->PollBitField (TechPtr->NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisDllShutdownSR, 0);
- return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
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