Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

26 files changed, 5525 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c
new file mode 100755
index 0000000000..0c04df82d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -0,0 +1,208 @@
+/**
+ * @file
+ *
+ * mfchi.c
+ *
+ * Feature Channel interleaving support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Chintlv)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfchi.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_ (0x10000 >> 10)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   MemFInterleaveChannels:
+ *
+ *  Applies DIMM channel interleaving if enabled, if not ganged mode, and
+ *  there are valid dimms in both channels.  Called once per Node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveChannels (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 DramBase;
+  UINT32 DctSelBase;
+  UINT32 HoleSize;
+  UINT32 HoleBase;
+  UINT32 HoleOffset;
+  UINT32 Dct0Size;
+  UINT32 Dct1Size;
+  UINT32 SmallerDct;
+  UINT8 DctSelIntLvAddr;
+  UINT8 DctSelHi;
+  UINT8 DctSelHiRngEn;
+  UINT32 HoleValid;
+
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+
+  DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr;
+  if (RefPtr->EnableChannelIntlv) {
+    HoleSize = 0;
+    HoleBase = 0;
+    if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
+      // HoleBase scaled from [47:16] to [47:26]
+      HoleBase = RefPtr->HoleBase >> 10;
+      HoleSize = _4GB_ - HoleBase;
+    }
+
+    MCTPtr = NBPtr->MCTPtr;
+
+    HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid);
+    if ((!MCTPtr->GangedMode) &&
+        (MCTPtr->DctData[0].Timings.DctMemSize != 0) &&
+        (MCTPtr->DctData[1].Timings.DctMemSize != 0)) {
+      // DramBase scaled [47:16] to [47:26]
+      DramBase = MCTPtr->NodeSysBase >> 10;
+      // Scale NodeSysLimit [47:16] to [47:26]
+      Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10;
+      Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset);
+      if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) {
+        Dct0Size -= HoleSize;
+      }
+      if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) {
+        Dct1Size -= HoleSize;
+      }
+      Dct1Size -= Dct0Size;
+      Dct0Size -= DramBase;
+
+       // Select the bigger size DCT to put in DctSelHi
+      DctSelHiRngEn = 1;
+      DctSelHi = 0;
+      SmallerDct = Dct1Size;
+      if (Dct1Size == Dct0Size) {
+        SmallerDct = 0;
+        DctSelHiRngEn = 0;
+      } else if (Dct1Size > Dct0Size) {
+        SmallerDct = Dct0Size;
+        DctSelHi = 1;
+      }
+
+      if (SmallerDct != 0) {
+        DctSelBase = (SmallerDct * 2) + DramBase;
+      } else {
+        DctSelBase = 0;
+      }
+      if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) {
+        DctSelBase += HoleSize;
+      }
+      IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader));
+      NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1);
+      NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn);
+      NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi);
+      NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr);
+      NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1);
+
+       // DctSelBaseOffset = DctSelBaseAddr - Interleaved region
+      NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct);
+
+       // Adjust DramHoleOffset
+      if (HoleValid != 0) {
+        HoleOffset = DramBase;
+        if ((DctSelBase < HoleBase) && (DctSelBase != 0)) {
+          HoleOffset += (DctSelBase - DramBase) >> 1;
+        }
+        HoleOffset += HoleSize;
+        NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3);
+      }
+    } else {
+      //
+      // Channel Interleaving is requested but cannot be enabled
+      //
+      PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, MCTPtr);
+    }
+
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h
new file mode 100755
index 0000000000..e8ffe19b97
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfchi.h
+ *
+ * Feature channel interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFCHI_H_
+#define _MFCHI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveChannels (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFCHI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c
new file mode 100755
index 0000000000..fb23c4f213
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -0,0 +1,331 @@
+/**
+ * @file
+ *
+ * mfcsi.c
+ *
+ * Feature bank interleaving support (AKA Chip Select Interleaving )
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Csintlv)
+ * @e \$Revision: 55148 $ @e \$Date: 2011-06-16 16:16:12 -0600 (Thu, 16 Jun 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/* This file contains functions for Chip Select interleaving */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mfcsi.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemFDctInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+CsIntSwap (
+  IN OUT   UINT32 *BaseMaskRegPtr,
+  IN       UINT8 EnChipSels,
+  IN       UINT8 LoBit,
+  IN       UINT8 HiBit
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function Applies DIMM bank (chip-select) interleaving if enabled
+ *      and if all criteria are met.  Interleaves chip-selects on page boundaries.
+ *      This function calls subfunctions that sets up CS interleaving on multiple Sockets
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  BOOLEAN RetFlag;
+
+  ASSERT (NBPtr != NULL);
+
+  RetFlag = FALSE;
+  if (NBPtr->RefPtr->EnableBankIntlv) {
+    if (NBPtr->MCTPtr->NodeMemSize) {
+      for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+        NBPtr->SwitchDCT (NBPtr, Dct);
+        RetFlag |= MemFDctInterleaveBanks (NBPtr);
+      }
+    }
+  }
+  return RetFlag;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function checks if bank interleaving has been enabled or not. If yes, it will
+ *     undo bank interleaving. Otherwise, it does nothing.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Bank interleaving has been enabled.
+ *     @return          FALSE - Bank interleaving has not been enabled.
+ */
+
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Cs;
+  UINT8 Dct;
+  UINT32 CSMask;
+  BOOLEAN CSIntlvEnabled;
+  BOOLEAN RetFlag;
+
+  ASSERT (NBPtr != NULL);
+
+  RetFlag = FALSE;
+
+  if (NBPtr->RefPtr->EnableBankIntlv) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize) {
+        CSIntlvEnabled = FALSE;
+        for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
+          if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
+            CSMask = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
+            if (((CSMask >> 5) & 0x1FF) != 0x1FF) {
+              CSIntlvEnabled = TRUE;
+              break;
+            }
+          }
+        }
+        if (CSIntlvEnabled) {
+          MemFDctInterleaveBanks (NBPtr);
+          RetFlag = TRUE;
+        }
+      }
+    }
+  }
+  return RetFlag;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function Applies DIMM bank (chip-select) interleaving if enabled
+ *      and if all criteria are met.  Interleaves chip-selects on page boundaries.
+ *      This function is run once per Socket
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Register bits have been swapped.
+ *     @return          FALSE - Register bits have not been swapped.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemFDctInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Cs;
+  UINT8 EnChipSels;
+  UINT8 BankEncd;
+  UINT8 BankEncd0;
+  UINT8 i;
+  UINT8 j;
+  UINT32 BankAddrReg;
+  UINT32 BaseRegS0;
+  UINT32 BaseRegS1;
+  UINT32 MaskReg;
+
+  ASSERT (NBPtr != NULL);
+
+  // Check if CS interleaving can be enabled
+  EnChipSels = 0;
+  BankEncd0 = 0xFF;
+  for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
+    if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 3) != 0) {
+      BankAddrReg = NBPtr->GetBitField (NBPtr, BFDramBankAddrReg);
+      BankEncd = (UINT8) ((BankAddrReg >> ((Cs / 2) * 4)) & 0xF);
+      if (BankEncd0 == 0xFF) {
+        BankEncd0 = BankEncd;
+      } else if (BankEncd0 != BankEncd) {
+        break;
+      }
+      if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
+        EnChipSels++;
+      }
+    }
+  }
+
+  // Swap Dram Base/Mask Addr to enable CS interleaving
+  if ((Cs == MAX_CS_PER_CHANNEL) && ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))) {
+    NBPtr->TechPtr->GetCSIntLvAddr (BankEncd0, &i, &j);
+    if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+      i++;
+      j++;
+    }
+
+    for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs += 2) {
+      BaseRegS0 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs);
+      BaseRegS1 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1);
+      if (((BaseRegS0 | BaseRegS1) & 1) != 0) {
+        // Swap Mask register bits
+        MaskReg = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
+        CsIntSwap (&MaskReg, EnChipSels, i, j);
+        NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (Cs / 2), MaskReg);
+
+        // Swap Base register bits
+        CsIntSwap (&BaseRegS0, EnChipSels, i, j);
+        NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs, BaseRegS0);
+        CsIntSwap (&BaseRegS1, EnChipSels, i, j);
+        NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1, BaseRegS1);
+      }
+    }
+    return TRUE;
+  } else {
+    //
+    // Bank Interleaving is requested but cannot be enabled
+    //
+    PutEventLog (AGESA_WARNING, MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    NBPtr->MCTPtr->ErrStatus[EsbBkIntDis] = TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This supporting function swaps Chip selects
+ *
+ *     @param[in,out]  *BaseMaskRegPtr   - Pointer to the Mask Register
+ *     @param[in]      *EnChipSels    - Chip Selects to Enable
+ *     @param[in]      *LoBit         - Lowest Bit
+ *     @param[in]      *HiBit         - Highest Bit
+ *
+ *
+ */
+
+VOID
+STATIC
+CsIntSwap (
+  IN OUT   UINT32 *BaseMaskRegPtr,
+  IN       UINT8 EnChipSels,
+  IN       UINT8 LoBit,
+  IN       UINT8 HiBit
+  )
+{
+  UINT8 BitDelta;
+  UINT32 TempHi;
+  UINT32 TempLo;
+  UINT32 AddrLoMask;
+  UINT32 AddrHiMask;
+
+  ASSERT (BaseMaskRegPtr != NULL);
+  ASSERT (HiBit > LoBit);
+
+  BitDelta = HiBit - LoBit;
+  AddrLoMask = (((UINT32)EnChipSels) - 1) << LoBit;
+  AddrHiMask = AddrLoMask << BitDelta;
+
+  TempHi = TempLo = *BaseMaskRegPtr;
+  TempLo &= AddrLoMask;
+  TempLo <<= BitDelta;     // move lower bits to upper bit position
+  TempHi &= AddrHiMask;
+  TempHi >>= BitDelta;     // move upper bits to lower bit position
+
+  *BaseMaskRegPtr &= ~AddrLoMask;
+  *BaseMaskRegPtr &= ~AddrHiMask;
+  *BaseMaskRegPtr |= TempLo | TempHi;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h
new file mode 100755
index 0000000000..621efb716c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfcsi.h
+ *
+ * Memory Controller
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFCSI_H_
+#define _MFCSI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFCSI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
new file mode 100755
index 0000000000..4a54516aa1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
@@ -0,0 +1,566 @@
+/**
+ * @file
+ *
+ * mfDMI.c
+ *
+ * Memory DMI table support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6529 $ @e \$Date: 2008-06-25 04:19:02 -0500 (Wed, 25 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_DMI_MFDMI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define MAX_DCTS_PER_DIE 2
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function gets DDR3 DMI information from SPD buffer and stores the info into heap
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8  i;
+  UINT8  Dimm;
+  UINT8  Socket;
+  UINT8  NodeId;
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT8  temp;
+  UINT8  MaxDimms;
+  UINT8  DimmIndex;
+  UINT8  MaxChannelsPerSocket;
+  UINT8  MaxDimmsPerChannel;
+  UINT8  FormFactor;
+  UINT16 TotalWidth;
+  UINT16 Speed;
+  UINT16 Capacity;
+  UINT16 Width;
+  UINT16 Rank;
+  UINT16 BusWidth;
+  UINT64 ManufacturerIdCode;
+  UINT32 MaxSockets;
+  UINT32 Address;
+
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DMI_INFO *DmiTable;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SpdDataStructure;
+
+  NBPtr = MemMainPtr->NBPtr;
+  MemPtr = MemMainPtr->MemPtr;
+  SpdDataStructure = MemPtr->SpdDataStructure;
+  MCTPtr = NBPtr->MCTPtr;
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Initialize local variables
+  MaxDimms = 0;
+
+  AGESA_TESTPOINT (TpProcMemDmi, &MemPtr->StdHeader);
+
+  ASSERT (NBPtr != NULL);
+
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
+      temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      MaxDimms = MaxDimms + temp;
+    }
+  }
+
+  // Allocate heap for memory DMI table 16, 17, 19, 20
+  AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 2 + sizeof (DMI_T17_MEMORY_TYPE);
+
+  AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR3
+    return FALSE;
+  }
+
+  DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
+  *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms;          // Number of memory devices
+  *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr3MemType;  // Memory type
+
+  //
+  // DMI TYPE 17
+  //
+  DimmIndex = 0;
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      //
+      // Get Node number and Dct number for this channel
+      //
+      ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
+      NodeId = ChannelPtr->MCTPtr->NodeId;
+      Dct = ChannelPtr->Dct;
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
+        DmiTable[DimmIndex].TotalWidth = 0xFFFF;
+        DmiTable[DimmIndex].DataWidth = 0xFFFF;
+        DmiTable[DimmIndex].MemorySize = 0xFFFF;
+        DmiTable[DimmIndex].Speed = 0;
+        DmiTable[DimmIndex].ManufacturerIdCode = 0;
+        DmiTable[DimmIndex].Attributes = 0;
+        DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].DimmPresent = 0;
+        DmiTable[DimmIndex].Socket = Socket;
+        DmiTable[DimmIndex].Channel = Channel;
+        DmiTable[DimmIndex].Dimm = Dimm;
+
+        for (i = 0; i < 4; i++) {
+          DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
+        }
+
+        for (i = 0; i < 18; i++) {
+          DmiTable[DimmIndex].PartNumber[i] = 0xFF;
+        }
+
+        if (SpdDataStructure[DimmIndex].DimmPresent) {
+          // Total Width (offset 08h) & Data Width (offset 0Ah)
+          TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8];
+          if ((TotalWidth & 0x18) == 0) {
+            // non ECC
+            if ((TotalWidth & 0x07) == 0) {
+              DmiTable[DimmIndex].TotalWidth = 8;           // 8 bits
+            } else if ((TotalWidth & 0x07) == 1) {
+              DmiTable[DimmIndex].TotalWidth  = 16;         // 16 bits
+            } else if ((TotalWidth & 0x07) == 2) {
+              DmiTable[DimmIndex].TotalWidth  = 32;         // 32 bits
+            } else if ((TotalWidth & 0x07) == 3) {
+              DmiTable[DimmIndex].TotalWidth  = 64;         // 64 bits
+            }
+            DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth ;
+          } else {
+            // ECC
+            if ((TotalWidth & 0x07) == 0) {
+              DmiTable[DimmIndex].TotalWidth  = 8 + 8;      // 8 bits
+            } else if ((TotalWidth & 0x07) == 1) {
+              DmiTable[DimmIndex].TotalWidth = 16 + 8;      // 16 bits
+            } else if ((TotalWidth & 0x07) == 2) {
+              DmiTable[DimmIndex].TotalWidth  = 32 + 8;     // 32 bits
+            } else if ((TotalWidth & 0x07) == 3) {
+              DmiTable[DimmIndex].TotalWidth  = 64 + 8;     // 64 bits
+            }
+            DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth - 8;
+          }
+
+          // Memory Size (offset 0Ch)
+          Capacity = 0;
+          BusWidth = 0;
+          Width = 0;
+          Rank = 0;
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[4];
+          if ((temp & 0x0F) == 0) {
+            Capacity = 0x0100;                              // 256M
+          } else if ((temp & 0x0F) == 1) {
+            Capacity = 0x0200;                              // 512M
+          } else if ((temp & 0x0F) == 2) {
+            Capacity = 0x0400;                              // 1G
+          } else if ((temp & 0x0F) == 3) {
+            Capacity = 0x0800;                              // 2G
+          } else if ((temp & 0x0F) == 4) {
+            Capacity = 0x1000;                              // 4G
+          } else if ((temp & 0x0F) == 5) {
+            Capacity = 0x2000;                              // 8G
+          } else if ((temp & 0x0F) == 6) {
+            Capacity = 0x4000;                              // 16G
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[8];
+          if ((temp & 0x07) == 0) {
+            BusWidth = 8;                                   // 8 bits
+          } else if ((temp & 0x07) == 1) {
+            BusWidth = 16;                                  // 16 bits
+          } else if ((temp & 0x07) == 2) {
+            BusWidth = 32;                                  // 32 bits
+          } else if ((temp & 0x07) == 3) {
+            BusWidth = 64;                                  // 64 bits
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
+          if ((temp & 0x07) == 0) {
+            Width = 4;                                      // 4 bits
+          } else if ((temp & 0x07) == 1) {
+            Width = 8;                                      // 8 bits
+          } else if ((temp & 0x07) == 2) {
+            Width = 16;                                     // 16 bits
+          } else if ((temp & 0x07) == 3) {
+            Width = 32;                                     // 32 bits
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
+          if (((temp >> 3) & 0x07) == 0) {
+            Rank = 1;                                       // 4 bits
+            DmiTable[DimmIndex].Attributes = 1;             // Single Rank Dimm
+          } else if (((temp >> 3) & 0x07) == 1) {
+            Rank = 2;                                       // 8 bits
+            DmiTable[DimmIndex].Attributes = 2;             // Dual Rank Dimm
+          } else if (((temp >> 3) & 0x07) == 2) {
+            Rank = 3;                                       // 16 bits
+          } else if (((temp >> 3) & 0x07) == 3) {
+            Rank = 4;                                       // 32 bits
+            DmiTable[DimmIndex].Attributes = 4;             // Quad Rank Dimm
+          }
+
+          DmiTable[DimmIndex].MemorySize = (UINT16) (Capacity / 8 * BusWidth / Width * Rank);
+
+          // Form Factor (offset 0Eh)
+          FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3];
+          if ((FormFactor & 0x01) == 0 || (FormFactor & 0x02) == 0) {
+            DmiTable[DimmIndex].FormFactor = 0x09;         // RDIMM or UDIMM
+          } else if ((FormFactor & 0x03) == 0) {
+            DmiTable[DimmIndex].FormFactor = 0x0D;         // SO-DIMM
+          }
+
+          // DIMM Present
+          DmiTable[DimmIndex].DimmPresent = 1;
+
+          // Speed (offset 15h)
+          Speed = (UINT16) SpdDataStructure[DimmIndex].Data[12];
+          if (Speed == 20) {
+            DmiTable[DimmIndex].Speed = 800;                // DDR3-800
+          } else if (Speed == 15) {
+            DmiTable[DimmIndex].Speed = 1066;               // DDR3-1066
+          } else if (Speed == 12) {
+            DmiTable[DimmIndex].Speed = 1333;               // DDR3-1333
+          } else if (Speed == 10) {
+            DmiTable[DimmIndex].Speed = 1600;               // DDR3-1600
+          }
+
+          // Manufacturer (offset 17h)
+          ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[118];
+          DmiTable[DimmIndex].ManufacturerIdCode = (ManufacturerIdCode << 8) | ((UINT64) SpdDataStructure[DimmIndex].Data[117]);
+
+          // Serial Number (offset 18h)
+          for (i = 0; i < 4; i++) {
+            DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 122];
+          }
+          // Part Number (offset 1Ah)
+          for (i = 0; i < 18; i++) {
+            DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 128];
+          }
+
+          // AGESA does NOT support this feature when bank interleaving is enabled.
+          if (!RefPtr->EnableBankIntlv) {
+          if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
+            Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0;
+              Address = Address >> 2;
+              DmiTable[DimmIndex].StartingAddr = Address;
+              DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400);
+            }
+          }
+        }  // Dimm present
+      }    // Dimm loop
+    }      // Channel loop
+  }          // Socket loop
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function gets DDR2 DMI information from SPD buffer and stores the info into heap
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8  i;
+  UINT8  Dimm;
+  UINT8  Socket;
+  UINT8  NodeId;
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT8  temp;
+  UINT8  MaxDimms;
+  UINT8  DimmIndex;
+  UINT8  MaxChannelsPerSocket;
+  UINT8  MaxDimmsPerChannel;
+  UINT8  FormFactor;
+  UINT8  Temp;
+  UINT8  Rank;
+  UINT16 TotalWidth;
+  UINT32 Speed;
+  UINT32 MaxSockets;
+  UINT32 Address;
+
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DMI_INFO *DmiTable;
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SpdDataStructure;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  MemPtr = MemMainPtr->MemPtr;
+  SpdDataStructure = MemPtr->SpdDataStructure;
+  MCTPtr = NBPtr->MCTPtr;
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Initialize local variables
+  MaxDimms = 0;
+
+  ASSERT (NBPtr != NULL);
+
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
+      temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      MaxDimms = MaxDimms + temp;
+    }
+  }
+
+  // Allocate heap for memory DMI table 16, 17, 19, 20
+  AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 3;
+
+  AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR2
+    return FALSE;
+  }
+
+  DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
+  *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms;          // Number of memory devices
+  *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr2MemType;  // Memory type
+
+  //
+  // DMI TYPE 17
+  //
+  DimmIndex = 0;
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      //
+      // Get Node number and Dct number for this channel
+      //
+      ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
+      NodeId = ChannelPtr->MCTPtr->NodeId;
+      Dct = ChannelPtr->Dct;
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
+        DmiTable[DimmIndex].TotalWidth = 0xFFFF;
+        DmiTable[DimmIndex].DataWidth = 0xFFFF;
+        DmiTable[DimmIndex].MemorySize = 0xFFFF;
+        DmiTable[DimmIndex].Speed = 0;
+        DmiTable[DimmIndex].ManufacturerIdCode = 0;
+        DmiTable[DimmIndex].Attributes = 0;
+        DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].DimmPresent = 0;
+
+        for (i = 0; i < 4; i++) {
+          DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
+        }
+
+        for (i = 0; i < 18; i++) {
+          DmiTable[DimmIndex].PartNumber[i] = 0xFF;
+        }
+
+        if (SpdDataStructure[DimmIndex].DimmPresent) {
+          // Total Width (offset 08h) & Data Width (offset 0Ah)
+          TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[13];
+          if ((TotalWidth & 0x04) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 4;          // 4 bits
+          } else if ((TotalWidth & 0x08) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 8;          // 8 bits
+          } else if ((TotalWidth & 0x10) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 16;         // 16 bits
+          } else if ((TotalWidth & 0x20) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 32;         // 32 bits
+          }
+          DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth;
+
+          // Memory Size (offset 0Ch), Attributes (offset 1Bh)
+          Rank = (UINT8) SpdDataStructure[DimmIndex].Data[5] & 0x07;
+          if (Rank == 0) {
+            DmiTable[DimmIndex].Attributes = 1;          // Single Rank Dimm
+          } else if (Rank == 1) {
+            DmiTable[DimmIndex].Attributes = 2;          // Dual Rank Dimm
+          } else if (Rank == 3) {
+            DmiTable[DimmIndex].Attributes = 4;          // Quad Rank Dimm
+          }
+
+          Temp = (UINT8) SpdDataStructure[DimmIndex].Data[31];
+          for (i = 0; i < 8; i++) {
+            if ((Temp & 0x01) == 1) {
+              DmiTable[DimmIndex].MemorySize = 0x80 * (i + 1) * (Rank + 1);
+            }
+            Temp = Temp >> 1;
+          }
+
+          // Form Factor (offset 0Eh)
+          FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20];
+          if ((FormFactor & 0x20) == 4) {
+            DmiTable[DimmIndex].FormFactor = 0x0D;       // SO-DIMM
+          } else {
+            DmiTable[DimmIndex].FormFactor = 0x09;       // RDIMM or UDIMM
+          }
+
+          // DIMM Present
+          DmiTable[DimmIndex].DimmPresent = 1;
+
+          // DIMM Index
+          DmiTable[DimmIndex].Socket = Socket;
+          DmiTable[DimmIndex].Channel = Channel;
+          DmiTable[DimmIndex].Dimm = Dimm;
+
+          // Speed (offset 15h)
+          Speed = NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFDramConfigHiReg);
+          Speed = Speed & 0x00000007;
+          if (Speed == 0) {
+            DmiTable[DimmIndex].Speed = 400;              // 400MHz
+          } else if (Speed == 1) {
+            DmiTable[DimmIndex].Speed = 533;              // 533MHz
+          } else if (Speed == 2) {
+            DmiTable[DimmIndex].Speed = 667;              // 667MHz
+          } else if (Speed == 3) {
+            DmiTable[DimmIndex].Speed = 800;              // 800MHz
+          }
+
+          // Manufacturer (offset 17h)
+          DmiTable[DimmIndex].ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[64];
+
+          // Serial Number (offset 18h)
+          for (i = 0; i < 4; i++) {
+            DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 95];
+          }
+
+          // Part Number (offset 1Ah)
+          for (i = 0; i < 18; i++) {
+            DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 73];
+          }
+
+          // AGESA does NOT support this feature when bank interleaving is enabled.
+          if (!RefPtr->EnableBankIntlv) {
+            if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
+              Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0;
+              Address = Address >> 2;
+              DmiTable[DimmIndex].StartingAddr = Address;
+              DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400);
+            }
+          }
+
+        }        // DIMM Present
+      }          // DIMM loop
+    }
+  }
+
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
new file mode 100755
index 0000000000..36d8a63f49
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
@@ -0,0 +1,315 @@
+/**
+ * @file
+ *
+ * mfecc.c
+ *
+ * Feature ECC initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/ECC)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfecc.h"
+#include "Filecode.h"
+#include "mfmemclr.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_FEAT_ECC_MFECC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#ifdef UNUSED_CODE
+UINT32
+STATIC
+MemFGetScrubAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+#endif
+
+VOID
+STATIC
+InitECCOverriedeStruct (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   ECC_OVERRIDE_STRUCT *pecc_override_struct
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function checks to see if ECC can be enabled on all nodes
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  MEM_SHARED_DATA *SharedPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  SharedPtr = NBPtr->SharedPtr;
+
+  if (MCTPtr->NodeMemSize != 0) {
+    if (SharedPtr->AllECC && MCTPtr->Status[SbEccDimms] && (MCTPtr->ErrCode < AGESA_ERROR)) {
+      // Clear all MCA reports before using scrubber
+      // to initialize ECC check bits
+      //
+      NBPtr->McaNbCtlReg = NBPtr->GetBitField (NBPtr, BFMcaNbCtlReg);
+      NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, 0);
+      NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, 0);
+      // In unganged mode, set DctDctIntlv
+      if (!NBPtr->Ganged) {
+        NBPtr->SetBitField (NBPtr, BFDctDatIntLv, 1);
+      }
+      //
+      // Set Ecc Symbol Size
+      //
+      NBPtr->SetEccSymbolSize (NBPtr);
+      // If ECC can be enabled on this node,
+      // set the master ECCen bit (according to setup)
+      //
+      NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
+      // Do mem clear on current node
+      MemFMctMemClr_Init (NBPtr);
+      return TRUE;
+    } else {
+      if (SharedPtr->AllECC) {
+        SharedPtr->AllECC = FALSE;
+      }
+      // ECC requested but cannot be enabled
+      MCTPtr->Status[SbEccDimms] = FALSE;
+      MCTPtr->ErrStatus[EsbDramECCDis] = TRUE;
+      PutEventLog (AGESA_ERROR, MEM_ERROR_ECC_DIS, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, MCTPtr);
+    }
+  }
+  return FALSE;
+}
+
+  /* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the ECC on all nodes
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInitECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Node;
+  UINT32 ScrubAddrRJ16;
+  DIE_STRUCT *MCTPtr;
+  ECC_OVERRIDE_STRUCT  ecc_override_struct;
+  InitECCOverriedeStruct (NBPtr, &ecc_override_struct);
+  IDS_OPTION_HOOK (IDS_ECC, &ecc_override_struct, &(NBPtr->MemPtr->StdHeader));
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  Node = MCTPtr->NodeId;
+
+  if (MCTPtr->Status[SbEccDimms]) {
+    // Program scrub address,
+    // let the scrub Addr be the Base of this Node
+    // Only enable Dram scrubber when there is memory on current node
+    //
+    NBPtr->SetBitField (NBPtr, BFScrubReDirEn, 0);
+    ScrubAddrRJ16 = (NBPtr->GetBitField (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
+    ScrubAddrRJ16 |= NBPtr->GetBitField (NBPtr, BFDramBaseHiReg0 + Node) << 24;
+    NBPtr->SetBitField (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
+    NBPtr->SetBitField (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
+
+    // Check if the input dram scrub rate is supported or not
+    ASSERT (ecc_override_struct.CfgScrubDramRate <= 0x16);
+    NBPtr->SetBitField (NBPtr, BFDramScrub, ecc_override_struct.CfgScrubDramRate);
+  }
+  // Scrub CTL for Dcache, L2, L3
+  // Check if the input L2 scrub rate is supported or not
+  ASSERT (ecc_override_struct.CfgScrubL2Rate <= 0x16);
+  NBPtr->SetBitField (NBPtr, BFL2Scrub, ecc_override_struct.CfgScrubL2Rate);
+  // Check if the input Dcache scrub rate is supported or not
+  ASSERT (ecc_override_struct.CfgScrubDcRate <= 0x16);
+  NBPtr->SetBitField (NBPtr, BFDcacheScrub, ecc_override_struct.CfgScrubDcRate);
+  // Do not enable L3 Scrub if F3xE8[L3Capable] is 0 or F3x188[DisableL3] is 1
+  if ((NBPtr->GetBitField (NBPtr, BFL3Capable) == 1) && (NBPtr->GetBitField (NBPtr, BFF3X188B8) == 0)) {
+    // Check if input L3 scrub rate is supported or not
+    ASSERT (ecc_override_struct.CfgScrubL3Rate <= 0x16);
+    NBPtr->SetBitField (NBPtr, BFL3Scrub, ecc_override_struct.CfgScrubL3Rate);
+  }
+
+  // Check if Dcache scrubber or L2 scrubber is enabled
+  if ((ecc_override_struct.CfgScrubL2Rate != 0) || (ecc_override_struct.CfgScrubDcRate!= 0)) {
+    // If ClkDivisor is deeper than divide-by-16
+    if (NBPtr->GetBitField (NBPtr, BFC1ClkDivisor) > 4) {
+      // Set it to divide-by-16
+      NBPtr->SetBitField (NBPtr, BFC1ClkDivisor, 4);
+    }
+  }
+
+  NBPtr->SetBitField (NBPtr, BFScrubReDirEn, ecc_override_struct.CfgEccRedirection);
+  NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, ecc_override_struct.CfgEccSyncFlood);
+  // Restore MCA reports after scrubber is done
+  // with initializing ECC check bits
+  NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, NBPtr->McaNbCtlReg);
+  return TRUE;
+}
+
+VOID
+STATIC
+InitECCOverriedeStruct (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   ECC_OVERRIDE_STRUCT *pecc_override_struct
+  )
+{
+  pecc_override_struct->CfgEccRedirection = UserOptions.CfgEccRedirection;
+  pecc_override_struct->CfgEccSyncFlood = UserOptions.CfgEccSyncFlood;
+  pecc_override_struct->CfgScrubDcRate = UserOptions.CfgScrubDcRate;
+
+  if (UserOptions.CfgScrubDramRate != 0xFF) {
+    pecc_override_struct->CfgScrubDramRate = UserOptions.CfgScrubDramRate;
+  } else {
+    if (NBPtr->MCTPtr->NodeMemSize <= 0x4000) {
+      pecc_override_struct->CfgScrubDramRate = 0x12; // 1 ~ 1 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x8000) {
+      pecc_override_struct->CfgScrubDramRate = 0x11; // 1 GB + 1 ~ 2 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x10000) {
+      pecc_override_struct->CfgScrubDramRate = 0x10; // 2 GB + 1 ~ 4 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x20000) {
+      pecc_override_struct->CfgScrubDramRate = 0x0F; // 4 GB + 1 ~ 8 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x40000) {
+      pecc_override_struct->CfgScrubDramRate = 0x0E; // 8 GB + 1 ~ 16 GB
+    } else {
+      pecc_override_struct->CfgScrubDramRate = 0x0D; //16 GB + 1 above
+    }
+  }
+
+  pecc_override_struct->CfgScrubL2Rate = UserOptions.CfgScrubL2Rate;
+  pecc_override_struct->CfgScrubL3Rate = UserOptions.CfgScrubL3Rate;
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This function gets the current 40-bit Scrub ADDR address, scaled to 32-bits,
+ *                of the specified Node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          Scrubber Address
+ */
+#ifdef UNUSED_CODE
+UINT32
+STATIC
+MemFGetScrubAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 ScrubAddrHi;
+  UINT32 ScrubAddrLo;
+  UINT32 ScrubAddrRJ16;
+
+  ASSERT (NBPtr != NULL);
+
+  ScrubAddrHi = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg);
+  ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg);
+  // Scrub Addr High again, detect 32-bit wrap
+  ScrubAddrRJ16 = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg);
+  if (ScrubAddrRJ16 != ScrubAddrHi) {
+    ScrubAddrHi = ScrubAddrRJ16;
+    ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg);
+  }
+  return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16));
+}
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h
new file mode 100755
index 0000000000..61877dae05
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfecc.h
+ *
+ * Feature ECC initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFECC_H_
+#define _MFECC_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInitECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFECC_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c
new file mode 100755
index 0000000000..8f7aaccae7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c
@@ -0,0 +1,173 @@
+/**
+ * @file
+ *
+ * mfemp.c
+ *
+ * Feature EMP initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/ECC)
+ * @e \$Revision: 6168 $ @e \$Date: 2008-05-28 22:26:15 -0500 (Wed, 28 May 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_ECC_MFEMP_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN       UINT32 Value
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes EMP (Enhanced Memory Protection)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  if (RefPtr->EnableEccFeature) {
+    if (NBPtr->GetBitField (NBPtr, BFEnhMemProtCap) == 0) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_SUPPORTED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPNotSupported] = TRUE;
+    } else if (RefPtr->EnableChannelIntlv || RefPtr->EnableBankIntlv || RefPtr->EnableBankSwizzle) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_CONFLICT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPConflict] = TRUE;
+    } else if ((!MCTPtr->GangedMode) &&
+               (!IsPowerOfTwo (MCTPtr->DctData[0].Timings.DctMemSize) &&
+                !IsPowerOfTwo (MCTPtr->DctData[1].Timings.DctMemSize))) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPDis] = TRUE;
+    } else {
+      // Reduce memory size to 7/8 of the original memory size
+      ASSERT ((MCTPtr->NodeMemSize % 8) == 0);
+      NBPtr->SetBitField (NBPtr, BFDramHoleValid, 0);
+      MCTPtr->NodeMemSize = (MCTPtr->NodeMemSize / 8) * 7;
+      NBPtr->HtMemMapInit (NBPtr);
+      NBPtr->CpuMemTyping (NBPtr);
+
+      // Enable EMP
+      NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
+
+      // Scrub CTL settings for Dcache, L2
+      NBPtr->SetBitField (NBPtr, BFL2Scrub, UserOptions.CfgScrubL2Rate);
+      NBPtr->SetBitField (NBPtr, BFDcacheScrub, UserOptions.CfgScrubDcRate);
+
+      NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, UserOptions.CfgEccSyncFlood);
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function checks to see if the input is power of two.
+ *
+ *     @param[in]    Value   - Value to check for power of two
+ *
+ *     @return          TRUE     - is power of two
+ *                      FALSE    - is not power of two
+ */
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN       UINT32 Value
+  )
+{
+  return (BOOLEAN) ((Value & (Value - 1)) == 0);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
new file mode 100755
index 0000000000..3bf0269ce0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -0,0 +1,194 @@
+/**
+ * @file
+ *
+ * mfdimmexclud.c
+ *
+ * Feature DIMM exclude.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/EXCLUDIMM)
+ * @e \$Revision: 6943 $ @e \$Date: 2008-08-206 20:51:30 +0800 (Sat, 26 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and disable Chip selects that fail training for each node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ReserveDCT;
+  UINT8 q;
+  BOOLEAN Flag;
+  BOOLEAN IsCSIntlvEnabled;
+  UINT16 CsTestFail;
+  DIE_STRUCT *MCTPtr;
+  BOOLEAN RetVal;
+
+  ASSERT (NBPtr != NULL);
+  ReserveDCT = NBPtr->Dct;
+  CsTestFail = 0;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.CsTestFail != 0) {
+      // When there is no new failed dimm that needs to be excluded, then no need to go through the process.
+      switch (NBPtr->SharedPtr->DimmExcludeFlag) {
+      case NORMAL:
+        // See there is new dimm that needs to be excluded
+        if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) {
+          CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
+        }
+        break;
+      case TRAINING:
+        // Do not do any dimm excluding during training
+        // Dimm exclude will be done at the end of training
+        break;
+      case END_TRAINING:
+        // Exclude all dimms that have failures during training
+        if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) ||
+            ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) {
+          CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
+        }
+        break;
+      default:
+        IDS_ERROR_TRAP;
+      }
+    }
+  }
+
+  if (CsTestFail != 0) {
+    IsCSIntlvEnabled = FALSE;
+    MCTPtr = NBPtr->MCTPtr;
+    MCTPtr->NodeMemSize = 0;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0;
+    NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+    NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0);
+
+    if (MCTPtr->GangedMode) {
+      // if ganged mode, disable all pairs of CS that fail.
+      NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail;
+    }
+
+    // if chip select interleaving has been enabled, need to undo it before remapping memory
+    if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) {
+      IsCSIntlvEnabled = TRUE;
+    }
+
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
+        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+          NBPtr->DCTPtr->Timings.DctMemSize = 0;
+
+          NBPtr->DCTPtr->Timings.CsEnabled = 0;
+          for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
+            NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
+          }
+
+          Flag = NBPtr->StitchMemory (NBPtr);
+          ASSERT (Flag == TRUE);
+        }
+      }
+    }
+
+    // Re-enable chip select interleaving when remapping is done.
+    if (IsCSIntlvEnabled) {
+      NBPtr->FeatPtr->InterleaveBanks (NBPtr);
+    }
+
+    RetVal = TRUE;
+  } else {
+    RetVal = FALSE;
+  }
+  NBPtr->SwitchDCT (NBPtr, ReserveDCT);
+  return RetVal;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
new file mode 100755
index 0000000000..3beae2bb6a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -0,0 +1,523 @@
+/**
+ * @file
+ *
+ * mfidendimm.c
+ *
+ * Translate physical system address to dimm identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat)
+ * @e \$Revision: 6314 $ @e \$Date: 2008-06-10 06:43:56 -0500 (Tue, 10 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "heapManager.h"
+#include "mfidendimm.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_DIE        2   ///< Max DCTs per die
+#define MAX_CHLS_PER_DCT        1   ///< Max Channels per DCT
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+STATIC
+MemFTransSysAddrToCS (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify,
+  IN       MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+UINT32
+STATIC
+MemFGetPCI (
+  IN   MEM_NB_BLOCK *NBPtr,
+  IN   UINT8 NodeID,
+  IN   UINT8 DctNum,
+  IN   BIT_FIELD_NAME BitFieldName
+  );
+
+UINT8
+STATIC
+MemFUnaryXOR (
+  IN   UINT32 address
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function identifies the dimm on which the given memory address locates.
+*
+*   @param[in, out]   *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
+*
+*   @retval           AGESA_SUCCESS - Successfully translate physical system address
+*                                     to dimm identification.
+*                     AGESA_BOUNDS_CHK - Targeted address is out of bound.
+*
+*/
+
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+  )
+{
+  UINT8 i;
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;             // Main Data block
+  MEM_NB_BLOCK *NBPtr;
+  MEM_DATA_STRUCT MemData;
+  LOCATE_HEAP_PTR LocHeap;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 Node;
+  UINT8 Dct;
+  UINT8 Die;
+  UINT8 DieCount;
+
+  LibAmdMemCopy (&(MemData.StdHeader), &(AmdDimmIdentify->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(AmdDimmIdentify->StdHeader));
+  mmData.MemPtr = &MemData;
+  RetVal = MemSocketScan (&mmData);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  // Search for AMD_MEM_AUTO_HANDLE on the heap first.
+  // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
+  LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, &AmdDimmIdentify->StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
+    AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, &AmdDimmIdentify->StdHeader) != AGESA_SUCCESS) {
+      PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK, 0, 0, 0, 0, &AmdDimmIdentify->StdHeader);
+      ASSERT(FALSE); // Could not allocate heap space for NB block for Identify DIMM
+      return AGESA_FATAL;
+    }
+    NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+    mmData.NBPtr = NBPtr;
+    // Construct each die.
+    for (Die = 0; Die < DieCount; Die ++) {
+      i = 0;
+      while (memNBInstalled[i].MemIdentifyDimmConstruct != 0) {
+        if (memNBInstalled[i].MemIdentifyDimmConstruct (&NBPtr[Die], &MemData, Die)) {
+          break;
+        }
+        i++;
+      };
+      if (memNBInstalled[i].MemIdentifyDimmConstruct == 0) {
+        PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM, Die, 0, 0, 0, &AmdDimmIdentify->StdHeader);
+        ASSERT(FALSE); // No Identify DIMM constructor found
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  if ((RetVal = MemFTransSysAddrToCS (AmdDimmIdentify, &mmData)) == AGESA_SUCCESS) {
+    // Translate Node, DCT and Chip select number to Socket, Channel and Dimm number.
+    Node = AmdDimmIdentify->SocketId;
+    Dct = AmdDimmIdentify->MemChannelId;
+    AmdDimmIdentify->SocketId = MemData.DiesPerSystem[Node].SocketId;
+    AmdDimmIdentify->MemChannelId = NBPtr[Node].GetSocketRelativeChannel (&NBPtr[Node], Dct, 0);
+    AmdDimmIdentify->DimmId /= 2;
+  }
+
+  return RetVal;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function translates the given physical system address to
+*   a node, channel select, chip select, bank, row, and column address.
+*
+*   @param[in, out]   *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
+*   @param[in, out]   *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
+*
+*   @retval           AGESA_SUCCESS - The chip select address is found
+*   @retval           AGESA_BOUNDS_CHK - Targeted address is out of bound.
+*
+*/
+AGESA_STATUS
+STATIC
+MemFTransSysAddrToCS (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify,
+  IN       MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  BOOLEAN CSFound;
+  BOOLEAN DctSelHiRngEn;
+  BOOLEAN DctSelIntLvEn;
+  BOOLEAN DctGangEn;
+  BOOLEAN HiRangeSelected;
+  BOOLEAN DramHoleValid;
+  BOOLEAN CSEn;
+  BOOLEAN SwapDone;
+  BOOLEAN IntLvRgnSwapEn;
+  UINT8 DctSelHi;
+  UINT8 DramEn;
+  UINT8 range;
+  UINT8 IntlvEn;
+  UINT8 IntlvSel;
+  UINT8 ILog;
+  UINT8 DctSelIntLvAddr;
+  UINT8 DctNum;
+  UINT8 cs;
+  UINT8 BadDramCs;
+  UINT8 spare;
+  UINT8 IntLvRgnBaseAddr;
+  UINT8 IntLvRgnLmtAddr;
+  UINT8 IntLvRgnSize;
+  UINT32 temp;
+  UINT32 DramHoleOffset;
+  UINT64 DramBase;
+  UINT64 DramLimit;
+  UINT64 DctSelBaseAddr;
+  UINT64 DctSelBaseOffset;
+  UINT64 ChannelAddr;
+  UINT64 CSBase;
+  UINT64 CSMask;
+  UINT64 InputAddr;
+  UINT64 ChannelOffset;
+  MEM_NB_BLOCK *NBPtr;
+
+  UINT64 SysAddr;
+  UINT8 *NodeID;
+  UINT8 *ChannelSelect;
+  UINT8 *ChipSelect;
+
+  SysAddr = AmdDimmIdentify->MemoryAddress;
+  NodeID = &(AmdDimmIdentify->SocketId);
+  ChannelSelect = &(AmdDimmIdentify->MemChannelId);
+  ChipSelect = &(AmdDimmIdentify->DimmId);
+  CSFound = FALSE;
+  ILog = 0;
+  NBPtr = mmPtr->NBPtr;
+
+  // Loop to determine the dram range
+  for (range = 0; range < mmPtr->DieCount; range ++) {
+    // DRAM Base
+    temp = MemFGetPCI (NBPtr, 0, 0, BFDramBaseReg0 + range);
+    DramEn = (UINT8) (temp & 0x3);
+    IntlvEn = (UINT8) ((temp >> 8) & 0x7);
+
+    DramBase = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramBaseHiReg0 + range) & 0xFF) << 40) |
+                 (((UINT64) temp & 0xFFFF0000) << 8);
+
+    // DRAM Limit
+    temp = MemFGetPCI (NBPtr, 0, 0, BFDramLimitReg0 + range);
+    *NodeID = (UINT8) (temp & 0x7);
+    IntlvSel = (UINT8) ((temp >> 8) & 0x7);
+    DramLimit = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramLimitHiReg0 + range) & 0xFF) << 40) |
+                  (((UINT64) temp << 8) | 0xFFFFFF);
+
+
+    if ((DramEn != 0) && (DramBase <= SysAddr) && (SysAddr <= DramLimit) &&
+        ((IntlvEn == 0) || (IntlvSel == ((SysAddr >> 12) & IntlvEn)))) {
+      // Determine the number of bit positions consumed by Node Interleaving
+      switch (IntlvEn) {
+
+      case 0x0:
+        ILog = 0;
+        break;
+
+      case 0x1:
+        ILog = 1;
+        break;
+
+      case 0x3:
+        ILog = 2;
+        break;
+
+      case 0x7:
+        ILog = 3;
+        break;
+
+      default:
+        IDS_ERROR_TRAP;
+      }
+
+      // F2x10C Swapped Interleaved Region
+      IntLvRgnSwapEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSwapEn);
+      if (IntLvRgnSwapEn) {
+        IntLvRgnBaseAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnBaseAddr);
+        IntLvRgnLmtAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnLmtAddr);
+        IntLvRgnSize = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSize);
+        ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
+        if (((SysAddr >> 34) == 0) &&
+          ((((SysAddr >> 27) >= IntLvRgnBaseAddr) && ((SysAddr >> 27) <= IntLvRgnLmtAddr))
+           || ((SysAddr >> 27) < IntLvRgnSize))) {
+          SysAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
+        }
+      }
+
+      // Extract variables from F2x110 DRAM Controller Select Low Register
+      DctSelHiRngEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHiRngEn);
+      DctSelHi = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHi);
+      DctSelIntLvEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvEn);
+      DctGangEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctGangEn);
+      DctSelIntLvAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvAddr);
+      DctSelBaseAddr = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseAddr) << 27;
+      DctSelBaseOffset = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseOffset) << 26;
+
+
+      // Determine if high DCT address range is being selected
+      if (DctSelHiRngEn && !DctGangEn && (SysAddr >= DctSelBaseAddr)) {
+        HiRangeSelected = TRUE;
+      } else {
+        HiRangeSelected = FALSE;
+      }
+
+      // Determine Channel
+      if (DctGangEn) {
+        *ChannelSelect = (UINT8) ((SysAddr >> 3) & 0x1);
+      } else if (HiRangeSelected) {
+        *ChannelSelect = DctSelHi;
+      } else if (DctSelIntLvEn && (DctSelIntLvAddr == 0)) {
+        *ChannelSelect = (UINT8) ((SysAddr >> 6) & 0x1);
+      } else if (DctSelIntLvEn && (((DctSelIntLvAddr >> 1) & 0x1) != 0)) {
+        temp = MemFUnaryXOR ((UINT32) ((SysAddr >> 16) & 0x1F));
+        if ((DctSelIntLvAddr & 0x1) != 0) {
+          *ChannelSelect = (UINT8) (((SysAddr >> 9) & 0x1) ^ temp);
+        } else {
+          *ChannelSelect = (UINT8) (((SysAddr >> 6) & 0x1) ^ temp);
+        }
+      } else if (DctSelIntLvEn) {
+        *ChannelSelect = (UINT8) ((SysAddr >> (12 + ILog)) & 0x1);
+      } else if (DctSelHiRngEn) {
+        *ChannelSelect = ~DctSelHi & 0x1;
+      } else {
+        *ChannelSelect = 0;
+      }
+      ASSERT (*ChannelSelect < NBPtr[*NodeID].DctCount);
+
+      DramHoleOffset = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleOffset) << 23;
+      DramHoleValid = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleValid);
+
+      // Determine base address offset
+      if (HiRangeSelected) {
+        if (((DctSelBaseAddr >> 32) == 0) && DramHoleValid && (SysAddr >= 0x100000000ull)) {
+          ChannelOffset = (UINT64) DramHoleOffset;
+        } else {
+          ChannelOffset = DctSelBaseOffset;
+        }
+      } else {
+        if (DramHoleValid && (SysAddr >= 0x100000000ull)) {
+          ChannelOffset = (UINT64) DramHoleOffset;
+        } else {
+          ChannelOffset = DramBase;
+        }
+      }
+
+      // Remove hoisting offset and normalize to DRAM bus addresses
+      ChannelAddr = SysAddr - ChannelOffset;
+
+      // Remove node interleaving
+      if (IntlvEn != 0) {
+        ChannelAddr = ((ChannelAddr >> (12 + ILog)) << 12) | (ChannelAddr & 0xFFF);
+      }
+
+      // Remove channel interleave
+      if (DctSelIntLvEn && !HiRangeSelected && !DctGangEn) {
+        if ((DctSelIntLvAddr & 1) != 1) {
+          // A[6] Select or Hash 6
+          ChannelAddr = ((ChannelAddr >> 7) << 6) | (ChannelAddr & 0x3F);
+        } else if (DctSelIntLvAddr == 1) {
+          // A[12]
+          ChannelAddr = ((ChannelAddr >> 13) << 12) | (ChannelAddr & 0xFFF);
+        } else {
+          // Hash 9
+          ChannelAddr = ((ChannelAddr >> 10) << 9) | (ChannelAddr & 0x1FF);
+        }
+      }
+
+      // Determine the Chip Select
+      for (cs = 0; cs < MAX_CS_PER_CHANNEL; ++ cs) {
+        DctNum = DctGangEn ? 0 : *ChannelSelect;
+
+        // Obtain the CS Base
+        temp = MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + cs);
+        CSEn = (BOOLEAN) (temp & 0x1);
+        CSBase = ((UINT64) temp & CS_REG_MASK) << 8;
+
+        // Obtain the CS Mask
+        CSMask = ((UINT64) MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSMask0Reg + (cs >> 1)) & CS_REG_MASK) << 8;
+
+        // Adjust the Channel Addr for easy comparison
+        InputAddr = ((ChannelAddr >> 8) & CS_REG_MASK) << 8;
+
+        if (CSEn && ((InputAddr & ~CSMask) == (CSBase & ~CSMask))) {
+          CSFound = TRUE;
+
+          *ChipSelect = cs;
+
+          temp = MemFGetPCI (NBPtr, *NodeID, 0, BFOnLineSpareControl);
+          SwapDone = (BOOLEAN) ((temp >> (1 + 2 * (*ChannelSelect))) & 0x1);
+          BadDramCs = (UINT8) ((temp >> (4 + 4 * (*ChannelSelect))) & 0x7);
+          if (SwapDone && (cs == BadDramCs)) {
+            // Find the spare rank for the channel
+            for (spare = 0; spare < MAX_CS_PER_CHANNEL; ++spare) {
+              if ((MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + spare) & 0x2) != 0) {
+                *ChipSelect = spare;
+                break;
+              }
+            }
+          }
+          ASSERT (*ChipSelect < MAX_CS_PER_CHANNEL);
+
+          break;
+        }
+      }
+    }
+    if (CSFound) {
+      break;
+    }
+  }
+
+  // last ditch sanity check
+  ASSERT (!CSFound || ((*NodeID < mmPtr->DieCount) && (*ChannelSelect < NBPtr[*NodeID].DctCount) && (*ChipSelect < MAX_CS_PER_CHANNEL)));
+  if (CSFound) {
+    return AGESA_SUCCESS;
+  } else {
+    return AGESA_BOUNDS_CHK;
+  }
+
+}
+
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function is the interface to call the PCI register access function
+*   defined in NB block.
+*
+*   @param[in]   *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK
+*   @param[in]   NodeID - Node ID number of the target Northbridge
+*   @param[in]   DctNum - DCT number if applicable, otherwise, put 0
+*   @param[in]   BitFieldName - targeted bitfield
+*
+*   @retval      UINT32 - 32 bits PCI register value
+*
+*/
+UINT32
+STATIC
+MemFGetPCI (
+  IN   MEM_NB_BLOCK *NBPtr,
+  IN   UINT8 NodeID,
+  IN   UINT8 DctNum,
+  IN   BIT_FIELD_NAME BitFieldName
+  )
+{
+  MEM_NB_BLOCK *LocalNBPtr;
+  // Get the northbridge pointer for the targeted node.
+  LocalNBPtr = &NBPtr[NodeID];
+  LocalNBPtr->Dct = DctNum;
+  // The caller of this function will take care of the ganged/unganged situation.
+  // So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum.
+  return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function returns an even parity bit (making the total # of 1's even)
+*   {0, 1} = number of set bits in argument is {even, odd}.
+*
+*   @param[in]   address - the address on which the parity bit will be calculated
+*
+*   @retval      UINT8 - parity bit
+*
+*/
+
+UINT8
+STATIC
+MemFUnaryXOR (
+  IN   UINT32 address
+  )
+{
+  UINT8 parity;
+  UINT8 index;
+  parity = 0;
+  for (index = 0; index < 32; ++ index) {
+    parity = (UINT8) (parity ^ (address & 0x1));
+    address = address >> 1;
+  }
+  return parity;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
new file mode 100755
index 0000000000..7ec7bc79d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
@@ -0,0 +1,108 @@
+/**
+ * @file
+ *
+ * mfidendimm.h
+ *
+ * Header file for address to dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 6609 $ @e \$Date: 2008-07-02 17:11:21 -0500 (Wed, 02 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFIDENDIMM_H_
+#define _MFIDENDIMM_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define CS_REG_MASK 0x1FF83FE0
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorLN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+#endif //_MFIDENDIMM_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
new file mode 100755
index 0000000000..e271834562
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -0,0 +1,148 @@
+/**
+ * @file
+ *
+ * mfrintlv.c
+ *
+ * Feature Region interleaving support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Intlvrgn)
+ * @e \$Revision: 9110 $ @e \$Date: 2008-10-28 01:16:14 +0800 (Tue, 28 Oct 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfintlvrn.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_RJ27 ((UINT32)4 << (30 - 27))
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   MemFInterleaveRegion:
+ *
+ *  Applies region interleaving if both DCTs have different size of memory, and
+ *  the channel interleaving region doesn't have UMA covered.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemFInterleaveRegion (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 TOM;
+  UINT32 TOM2;
+  UINT32 TOMused;
+  UINT32 UmaBase;
+  UINT32 DctSelBase;
+  S_UINT64 SMsr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  MemPtr = NBPtr->MemPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16);
+
+  //TOM scaled from [47:0] to [47:27]
+  LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
+
+  //TOM2 scaled from [47:0] to [47:27]
+  LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
+
+  TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM;
+
+  if (UmaBase != 0) {
+    //Check if channel interleaving is enabled ? if so, go to next step.
+    if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) {
+      DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr);
+      //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1.
+      if (DctSelBase != 0) {
+        //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA.
+        if (DctSelBase < TOMused) {
+          IDS_HDT_CONSOLE ("@\tStarting Interleave Region for Socket %d Die %d\n", NBPtr->MCTPtr->SocketId, NBPtr->Node);
+          NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused);
+        }
+      }
+    }
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
new file mode 100755
index 0000000000..77070f7947
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfintlvrn.h
+ *
+ * Feature region interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 9110 $ @e \$Date: 2008-10-28 01:16:14 +0800 (Tue, 28 Oct 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFINTLVRN_H_
+#define _MFINTLVRN_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemFInterleaveRegion (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFINTLVRN_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c
new file mode 100755
index 0000000000..ea1248cd56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -0,0 +1,167 @@
+/**
+ * @file
+ *
+ * lvddr3.c
+ *
+ * Voltage change for DDR3 DIMMs.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/LVDDR3)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE
+/* features */
+#include "mflvddr3.h"
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculate the common lowest voltage supported by all DDR3
+ *   DIMMs in the system. This function only needs to be called on BSP.
+ *
+ *   @param[in, out]    *NBPtr - Pointer to NB block
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFLvDdr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_TECH_BLOCK  *TechPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 Dimm;
+  UINT8 *SpdBufferPtr;
+  UINT8 VDDByte;
+  UINT8 VoltageMap;
+
+  mmSharedPtr = NBPtr->SharedPtr;
+  TechPtr = NBPtr->TechPtr;
+  VoltageMap = 0xFF;
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+        if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) {
+          // SPD byte 6: Module Nominal Voltage, VDD
+          // 1.5v - bit 0
+          // 1.35v - bit 1
+          // 1.2v - bit 2
+          VDDByte = SpdBufferPtr[MNVVDD];
+          // Reverse the 1.5V operable bit. So its encoding can be consistent
+          // with that of 1.35V and 1.25V operable bit.
+          VDDByte ^= 1;
+          ASSERT (VDDByte != 0);
+
+          if (mmSharedPtr->VoltageMap != 0) {
+            // Get the common supported voltage map
+            VoltageMap &= VDDByte;
+          } else {
+            // This is the second execution of all the loop as no common voltage is found
+            if (VDDByte == (1 << VOLT1_5)) {
+              // Always exclude 1.5V dimm if no common voltage is found
+              ChannelPtr->DimmExclude |= (UINT16) 1 << Dimm;
+            }
+          }
+        }
+      }
+      if (mmSharedPtr->VoltageMap == 0) {
+        NBPtr->DCTPtr->Timings.DimmExclude |= ChannelPtr->DimmExclude;
+      }
+    }
+  }
+
+  if (mmSharedPtr->VoltageMap != 0) {
+    mmSharedPtr->VoltageMap &= VoltageMap;
+  }
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.h
new file mode 100755
index 0000000000..0d5428c560
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * mflvddr3.h
+ *
+ * Header file for DDR3 DIMMs voltage configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 6609 $ @e \$Date: 2008-07-02 17:11:21 -0500 (Wed, 02 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFLVDDR3_H_
+#define _MFLVDDR3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MNVVDD 6
+#define LOWEST_VOLT_BIT 2
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFLvDdr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+);
+
+#endif //_MFLVDDR3_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
new file mode 100755
index 0000000000..8a07406c37
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -0,0 +1,147 @@
+/**
+ * @file
+ *
+ * mfmemclr.c
+ *
+ * Feature function for memory clear operation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Memclr)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfmemclr.h"
+#include "Ids.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Initiates memory clear operation on one node with Dram on it.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemFMctMemClr_Init (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcMemMemClr, &NBPtr->MemPtr->StdHeader);
+  if (NBPtr->RefPtr->EnableMemClr == TRUE) {
+    if (NBPtr->MCTPtr->NodeMemSize != 0) {
+      if (!NBPtr->MemCleared) {
+        NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE);
+        if (NBPtr->GetBitField (NBPtr, BFDramEnabled) == 1) {
+          NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+          NBPtr->SetBitField (NBPtr, BFMemClrInit, 1);
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Ensures memory clear operation has completed on one node with Dram on it.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemFMctMemClr_Sync (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 MicroSecondToWait;
+
+  MicroSecondToWait = 0;
+  if (NBPtr->RefPtr->EnableMemClr == TRUE) {
+    if (NBPtr->MCTPtr->NodeMemSize != 0) {
+      // Calculate Timeout value:
+      // Timeout (in microsecond) = Memory Size * 1.5 ns / 8 Byte * 4 (Margin) * 1000 (change mini-second to us)
+      // NodeMemSize is system address right shifted by 16, so shift it 4 bits to right to convert it to MB.
+      // 1.5 / 8 * 4 * 1000 = 750
+      MicroSecondToWait = (NBPtr->MCTPtr->NodeMemSize >> 4) * 750;
+
+      if (!NBPtr->MemCleared) {
+        NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, MicroSecondToWait, FALSE);
+        NBPtr->PollBitField (NBPtr, BFMemCleared, 1, MicroSecondToWait, FALSE);
+        NBPtr->SetBitField (NBPtr, BFDramBaseAddr, NBPtr->MCTPtr->NodeSysBase >> (27 - 16));
+        NBPtr->MemCleared = TRUE;
+      }
+    }
+  }
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c
new file mode 100755
index 0000000000..c57a74b606
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c
@@ -0,0 +1,239 @@
+/**
+ * @file
+ *
+ * mfndi.c
+ *
+ * Feature applies Node memory interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Ndintlv)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  *
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+  *       its contributors may be used to endorse or promote products derived
+  *       from this software without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mport.h"
+#include "mfndi.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_ (0x10000)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFCheckInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Perform a check to see if node interleaving can be enabled on each node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Node interleaving can be enabled.
+ *     @return          FALSE - Node interleaving cannot be enabled.
+ */
+
+BOOLEAN
+MemFCheckInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+
+  if (MCTPtr->NodeMemSize != 0) {
+    if (!NBPtr->SharedPtr->NodeIntlv.IsValid) {
+      NBPtr->SharedPtr->NodeIntlv.NodeMemSize = MCTPtr->NodeMemSize;
+      NBPtr->SharedPtr->NodeIntlv.Dct0MemSize = MCTPtr->DctData[0].Timings.DctMemSize;
+      NBPtr->SharedPtr->NodeIntlv.IsValid = TRUE;
+    } else {
+      if ((NBPtr->SharedPtr->NodeIntlv.NodeMemSize != MCTPtr->NodeMemSize) ||
+          (NBPtr->SharedPtr->NodeIntlv.Dct0MemSize != MCTPtr->DctData[0].Timings.DctMemSize)) {
+        return FALSE;
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Applies Node memory interleaving for each node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 NodeCnt;
+  UINT8 BitShift;
+  UINT32 MemSize;
+  UINT32 Dct0MemSize;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  UINT32 HoleBase;
+  UINT32 HoleSize;
+  UINT32 HoleOffset;
+  S_UINT64 SMsr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
+    HoleBase = RefPtr->HoleBase;
+    HoleSize = _4GB_ - HoleBase;
+  } else {
+    HoleBase = 0;
+    HoleSize = 0;
+  }
+
+  NodeCnt = NBPtr->SharedPtr->NodeIntlv.NodeCnt;
+  Dct0MemSize = NBPtr->SharedPtr->NodeIntlv.Dct0MemSize;
+  MemSize = NBPtr->SharedPtr->NodeIntlv.NodeMemSize;
+
+  BitShift = LibAmdBitScanForward (NodeCnt);
+  Dct0MemSize <<= BitShift;
+  if (HoleSize != 0) {
+    RefPtr->GStatus[GsbHWHole] = TRUE;
+    HoleOffset = HoleSize;
+    if (Dct0MemSize >= HoleBase) {
+      Dct0MemSize += HoleSize;
+    } else {
+      HoleOffset += Dct0MemSize;
+    }
+  } else {
+    HoleOffset = 0;
+  }
+
+  MemSize = (MemSize << BitShift) + HoleSize;
+
+  MCTPtr->NodeSysBase = 0;
+  MCTPtr->NodeSysLimit = MemSize - 1;
+  RefPtr->SysLimit = MemSize - 1;
+
+  // When node interleaving is enabled with larger than 1012GB memory,
+  // system memory limit will be lowered to fill in HT reserved region.
+  // TOP_MEM2 was set in CpuMemTyping and needs to be updated as well.
+  if (RefPtr->SysLimit >= HT_REGION_BASE_RJ16) {
+    if (RefPtr->LimitMemoryToBelow1Tb) {
+      SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16);
+      SMsr.lo = HT_REGION_BASE_RJ16 << 16;
+    } else {
+      SMsr.hi = MemSize >> (32 - 16);
+      SMsr.lo = MemSize << 16;
+    }
+    LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    IDS_HDT_CONSOLE ("TOP_MEM2: %08lx0000\n", MemSize);
+    RefPtr->Sub1THoleBase =  HT_REGION_BASE_RJ16;
+    RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1;
+  } else {
+    RefPtr->Sub1THoleBase =  RefPtr->SysLimit + 1;
+  }
+
+  NBPtr->SetBitField (NBPtr, BFDramIntlvSel, NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel);
+  NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+  NBPtr->SetBitField (NBPtr, BFDramIntlvEn, NodeCnt - 1);
+  NBPtr->SetBitField (NBPtr, BFDramLimitAddr, (MemSize - 1) >> (27 - 16));
+
+  if (HoleSize != 0) {
+    MCTPtr->Status[SbHWHole] = TRUE;
+    // DramHoleBase will be set when sync address map to other nodes.
+    NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset >> (23 - 16));
+    NBPtr->SetBitField (NBPtr, BFDramHoleValid, 1);
+  }
+
+  if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
+    NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, Dct0MemSize >> (27 - 16));
+    NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, Dct0MemSize >> (26 - 16));
+  }
+
+  NodeSysBase = NodeCnt - 1;
+  NodeSysLimit = ((MemSize - 1)& 0xFFFFFF00) | NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel;
+  NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
+  NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
+  NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit;
+
+  NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel++;
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h
new file mode 100755
index 0000000000..20c1f8dc77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * mfndi.h
+ *
+ * Feature node interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+#ifndef _MFNDI_H_
+#define _MFNDI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFNDI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
new file mode 100755
index 0000000000..659ba9d776
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -0,0 +1,168 @@
+/**
+ * @file
+ *
+ * mfodthermal.c
+ *
+ * On Dimm thermal management.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat)
+ * @e \$Revision: 6314 $ @e \$Date: 2008-06-10 06:43:56 -0500 (Tue, 10 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "mfodthermal.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function does On-Dimm thermal management.
+ *
+ *   @param[in, out]   *NBPtr - Pointer to the MEM_NB_BLOCK.
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFOnDimmThermal (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  UINT8 Dct;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  UINT8 *SpdBufferPtr;
+  UINT8 ThermalOp;
+  BOOLEAN ODTSEn;
+  BOOLEAN ExtendTmp;
+
+  ODTSEn = FALSE;
+  ExtendTmp = FALSE;
+
+  ASSERT (NBPtr != NULL);
+  MemPtr = NBPtr->MemPtr;
+  AGESA_TESTPOINT (TpProcMemOnDimmThermal, &MemPtr->StdHeader);
+
+  if (NBPtr->MCTPtr->NodeMemSize != 0) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      // Only go through the DCT if it is not disabled.
+      if (NBPtr->GetBitField (NBPtr, BFDisDramInterface) == 0) {
+        ChannelPtr = NBPtr->ChannelPtr;
+        // If Ganged mode is enabled, need to go through all dram devices on both DCTs.
+        if (!NBPtr->Ganged || (NBPtr->Dct != 1)) {
+          ODTSEn = TRUE;
+          ExtendTmp = TRUE;
+        }
+        for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
+          if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, i)) {
+            // Check byte 31: thermal and refresh option.
+            ThermalOp = SpdBufferPtr[THERMAL_OPT];
+            // Bit 3: ODTS readout
+            if (!((ThermalOp >> 3) & 1)) {
+              ODTSEn = FALSE;
+            }
+            // Bit 0: Extended Temperature Range.
+            if (!(ThermalOp & 1)) {
+              ExtendTmp = FALSE;
+            }
+          }
+        }
+
+        if (!NBPtr->Ganged || (NBPtr->Dct == 1)) {
+          // If in ganged mode, need to switch back to DCT0 to set the registers.
+          if (NBPtr->Ganged) {
+            NBPtr->SwitchDCT (NBPtr, 0);
+            ChannelPtr = NBPtr->ChannelPtr;
+          }
+          // If all dram devices on a DCT support ODTS
+          if (ODTSEn) {
+            NBPtr->SetBitField (NBPtr, BFODTSEn, 1);
+          }
+
+          ChannelPtr->ExtendTmp = ExtendTmp;
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
new file mode 100755
index 0000000000..1ea7c2490b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * mfodthermal.h
+ *
+ * Header file for On-Dimm thermal management.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 6609 $ @e \$Date: 2008-07-02 17:11:21 -0500 (Wed, 02 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFODTHERMAL_H_
+#define _MFODTHERMAL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define THERMAL_OPT 31
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFOnDimmThermal (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif //_MFODTHERMAL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c
new file mode 100755
index 0000000000..1aac4f44f8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c
@@ -0,0 +1,166 @@
+/**
+ * @file
+ *
+ * mfspr.c
+ *
+ * Feature enable online spare
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Olspare)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfspr.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Enable online spare on current node if it is requested.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFOnlineSpare (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 q;
+  UINT8  Value8;
+  BOOLEAN Flag;
+  BOOLEAN OnlineSprEnabled[MAX_CHANNELS_PER_SOCKET];
+
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+  Flag = FALSE;
+  if (RefPtr->EnableOnLineSpareCtl != 0) {
+    RefPtr->GStatus[GsbEnDIMMSpareNW] = TRUE;
+    MCTPtr = NBPtr->MCTPtr;
+
+    // Check if online spare can be enabled on current node
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      ASSERT (Dct < sizeof (OnlineSprEnabled));
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      OnlineSprEnabled[Dct] = FALSE;
+      if ((MCTPtr->GangedMode == 0) || (MCTPtr->Dct == 0)) {
+        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+          // Make sure at least two chip-selects are available
+          Value8 = LibAmdBitScanReverse (NBPtr->DCTPtr->Timings.CsEnabled);
+          if (Value8 > LibAmdBitScanForward (NBPtr->DCTPtr->Timings.CsEnabled)) {
+            OnlineSprEnabled[Dct] = TRUE;
+            Flag = TRUE;
+          } else {
+            PutEventLog (AGESA_ERROR, MEM_ERROR_DIMM_SPARING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            MCTPtr->ErrStatus[EsbSpareDis] = TRUE;
+          }
+        }
+      }
+    }
+
+    // If we don't have spared rank on any DCT, we don't run the rest part of the code.
+    if (!Flag) {
+      return FALSE;
+    }
+
+    MCTPtr->NodeMemSize = 0;
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (OnlineSprEnabled[Dct]) {
+        // Only run StitchMemory if we need to set a spare rank.
+        NBPtr->DCTPtr->Timings.DctMemSize = 0;
+        for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
+          NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
+        }
+        Flag = NBPtr->StitchMemory (NBPtr);
+        ASSERT (Flag == TRUE);
+      } else if ((MCTPtr->GangedMode == 0) && (NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
+        // Otherwise, need to adjust the memory size on the node.
+        MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
+        MCTPtr->NodeSysLimit = MCTPtr->NodeMemSize - 1;
+      }
+    }
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h
new file mode 100755
index 0000000000..c6fc4bcbaf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * mfspr.h
+ *
+ * Feature enable Online spare
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MFSPR_H_
+#define _MFSPR_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFOnlineSpare (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFSPR_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
new file mode 100755
index 0000000000..8f124340e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -0,0 +1,284 @@
+/**
+ * @file
+ *
+ * mfParallelTraining.c
+ *
+ * This is the parallel training feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/PARTRN)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "mfParallelTraining.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
+
+/*-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *    This is the main function to perform parallel training on all nodes.
+ *    This is the routine which will run on the remote AP.
+ *
+ *     @param[in,out]   *EnvPtr   - Pointer to the Training Environment Data
+ *     @param[in,out]   *StdHeader   - Pointer to the Standard Header of the AP
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFParallelTraining (
+  IN OUT   REMOTE_TRAINING_ENV *EnvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  MEM_PARAMETER_STRUCT ParameterList;
+  MEM_NB_BLOCK NB;
+  MEM_TECH_BLOCK TB;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  UINT8 p;
+  UINT8 i;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 *BufferPtr;
+  UINT8 DctCount;
+  UINT8 ChannelCount;
+  UINT8 RowCount;
+  UINT8 ColumnCount;
+  UINT16 SizeOfNewBuffer;
+  AP_DATA_TRANSFER ReturnData;
+
+  //
+  // Initialize Parameters
+  //
+  ReturnData.DataPtr = NULL;
+  ReturnData.DataSizeInDwords = 0;
+  ReturnData.DataTransferFlags = 0;
+
+  ASSERT (EnvPtr != NULL);
+  //
+  // Replace Standard header of a AP
+  //
+  LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
+
+  IDS_HDT_CONSOLE_INIT (StdHeader);
+
+  //
+  //  Allocate buffer for training data
+  //
+  BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
+  DctCount = EnvPtr->DieStruct.DctCount;
+  BufferPtr += sizeof (DIE_STRUCT);
+  ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
+  BufferPtr += DctCount * sizeof (DCT_STRUCT);
+  RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
+  ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
+
+  SizeOfNewBuffer = sizeof (DIE_STRUCT) +
+                    DctCount * (
+                      sizeof (DCT_STRUCT) + (
+                        ChannelCount * (
+                          sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
+                            RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
+                            (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
+                          )
+                        )
+                      )
+                    );
+  AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    BufferPtr = AllocHeapParams.BufferPtr;
+    LibAmdMemCopy ( BufferPtr,
+                    &(EnvPtr->DieStruct),
+                    sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
+                    StdHeader
+                  );
+
+    //
+    //  Fix up pointers
+    //
+    MCTPtr = (DIE_STRUCT *) BufferPtr;
+    BufferPtr += sizeof (DIE_STRUCT);
+    MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
+    BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
+    for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+      MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
+      BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
+      for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
+        MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
+        MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
+      }
+    }
+    NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
+    BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
+
+    ReturnData.DataPtr = AllocHeapParams.BufferPtr;
+    ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
+    ReturnData.DataTransferFlags = 0;
+
+    //
+    // Allocate Memory for the MEM_DATA_STRUCT we will use
+    //
+    AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+    AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+      MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
+
+      LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
+
+      //
+      // Copy Parameters from environment
+      //
+      ParameterList.HoleBase = EnvPtr->HoleBase;
+      ParameterList.BottomIo = EnvPtr->BottomIo;
+      ParameterList.UmaSize = EnvPtr->UmaSize;
+      ParameterList.SysLimit = EnvPtr->SysLimit;
+      ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
+      ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
+      MemPtr->ParameterListPtr = &ParameterList;
+
+      for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+        MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
+      }
+
+      MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
+      //
+      // Create Local NBBlock and Tech Block
+      //
+      EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
+      NB.RefPtr = &ParameterList;
+      NB.MemPtr = MemPtr;
+      i = 0;
+      while (memTechInstalled[i] != NULL) {
+        if (memTechInstalled[i] (&TB, &NB)) {
+          break;
+        }
+        i++;
+      }
+      NB.TechPtr = &TB;
+      NB.TechBlockSwitch (&NB);
+
+      //
+      // Setup CPU Mem Type MSRs on the AP
+      //
+      NB.CpuMemTyping (&NB);
+
+      IDS_HDT_CONSOLE ("!Node %d\n", NB.Node);
+      //
+      // Call Technology Specific Training routine
+      //
+      NB.TrainingFlow (&NB);
+      //
+      // Copy training data to ReturnData buffer
+      //
+      LibAmdMemCopy ( BufferPtr,
+                      MCTPtr->DctData[0].ChData[0].RcvEnDlys,
+                      ((DctCount * ChannelCount) * (
+                         (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
+                         (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
+                        )
+                      ),
+                      StdHeader);
+
+      HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+      //
+      // Restore pointers
+      //
+      for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+        for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
+          MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
+          MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
+
+          MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
+        }
+        MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
+      }
+      MCTPtr->DctData = EnvPtr->DieStruct.DctData;
+    }
+
+    //
+    // Signal to BSP that training is complete and Send Results
+    //
+    ASSERT (ReturnData.DataPtr != NULL);
+    ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
+
+    //
+    // Clean up and exit.
+    //
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
+  } else {
+    MCTPtr = &EnvPtr->DieStruct;
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
+  }
+  IDS_HDT_CONSOLE_EXIT (StdHeader);
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
new file mode 100755
index 0000000000..76941ccb3f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mfStandardTraining.c
+ *
+ * This is the standard training routine which performs all training from the BSP
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/PARTRN)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "mfStandardTraining.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This is the main function to perform memory training on all nodes from
+ *       the BSP only.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFStandardTraining (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  ASSERT (NBPtr != NULL);
+
+  NBPtr->TrainingFlow (NBPtr);
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c
new file mode 100755
index 0000000000..df154fab4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c
@@ -0,0 +1,753 @@
+/**
+ * @file
+ *
+ * mfs3.c
+ *
+ * Main S3 resume memory Entrypoint file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/FEAT/S3)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "heapManager.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_S3_MFS3_FILECODE
+
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the main memory entry point for the S3 resume sequence
+ *      Requirements:
+ *
+ *      Run-Time Requirements:
+ *      1. Complete Hypertransport Bus Configuration
+ *      4. BSP in Big Real Mode
+ *      5. Stack available
+ *
+ *      @param[in]  *StdHeader - Config handle for library and services
+ *
+ *      @return     AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+AmdMemS3Resume (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  UINT8 Die;
+  UINT8 DieCount;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  //---------------------------------------------
+  //1. Errata Before resume sequence
+  //2. S3 Resume sequence
+  //3. Errata After resume sequence
+  //---------------------------------------------
+  for (Die = 0; Die < DieCount; Die ++) {
+    if (S3NBPtr[Die].MemS3Resume (&S3NBPtr[Die], Die) == 0) {
+      return AGESA_FATAL;
+    }
+    S3NBPtr[Die].MemS3RestoreScrub (S3NBPtr[Die].NBPtr, Die);
+  }
+
+  HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function deallocates heap space allocated in memory S3 resume.
+ *
+ *      @param[in]  *StdHeader - Config handle for library and services
+ *
+ *      @return     AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3Deallocate (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  AGESA_STATUS tempRetVal;
+
+  RetVal = AGESA_SUCCESS;
+  tempRetVal = HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  tempRetVal = HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  RetVal = HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  RetVal = HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the entrance to get device list for memory registers.
+ *
+ *      @param[in, out]  **DeviceBlockHdrPtr - Pointer to the memory containing the
+ *                                             device descriptor list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetDeviceList (
+  IN OUT   DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 i;
+  UINT16 BufferSize;
+  UINT32 BufferOffset;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  MEM_MAIN_DATA_BLOCK mmData;
+  UINT8 Die;
+  UINT8 DieCount;
+  AGESA_STATUS RetVal;
+  AGESA_BUFFER_PARAMS AllocBufferParams;
+  DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
+  BufferSize = 0;
+
+  LibAmdMemCopy (&AllocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  // Get the mask bit and the register list for node that presents
+  for (Die = 0; Die < DieCount; Die ++) {
+    S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+    S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+    BufferSize = BufferSize + S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+  }
+
+  // Base on the size of the device list, apply for a buffer for it.
+  AllocBufferParams.BufferLength = BufferSize + sizeof (DEVICE_BLOCK_HEADER);
+  AllocBufferParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE;
+  AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader);
+  if (AgesaAllocateBuffer (0, &AllocBufferParams) != AGESA_SUCCESS) {
+    return AGESA_FATAL;
+  }
+  AGESA_TESTPOINT (TpIfAfterAllocateMemoryS3SaveBuffer, StdHeader);
+
+  *DeviceBlockHdrPtr = (DEVICE_BLOCK_HEADER *) AllocBufferParams.BufferPointer;
+  (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocBufferParams.BufferLength;
+
+  // Copy device list on the stack to the heap.
+  BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT32) AllocBufferParams.BufferPointer;
+  for (Die = 0; Die < DieCount; Die ++) {
+    for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+      // Copy PCI device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
+      }
+      // Copy conditional PCI device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+      }
+      // Copy MSR device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
+      }
+      // Copy conditional MSR device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+      }
+    }
+  }
+
+  return RetVal;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initialize the northbridge block and apply for heap space
+ *      before any function call is made to memory component during S3 resume.
+ *
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3ResumeInitNB (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  UINT8 Die;
+  UINT8 DieCount;
+  UINT8 SpecialCaseHeapSize;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  S3_SPECIAL_CASE_HEAP_HEADER SpecialHeapHeader[MAX_NODES_SUPPORTED];
+
+  SpecialCaseHeapSize = 0;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  //--------------------------------------------------
+  //  Apply for heap space for special case registers
+  //--------------------------------------------------
+  for (Die = 0; Die < DieCount; Die ++) {
+    // Construct the header for the special case heap.
+    SpecialHeapHeader[Die].Node = S3NBPtr[Die].NBPtr->Node;
+    SpecialHeapHeader[Die].Offset = SpecialCaseHeapSize + (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER)));
+    SpecialCaseHeapSize = SpecialCaseHeapSize + S3NBPtr->MemS3SpecialCaseHeapSize;
+  }
+  AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))) + SpecialCaseHeapSize;
+  AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS, S3NBPtr[Die].NBPtr->Node, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, S3NBPtr[Die].NBPtr->MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap space for "S3_SPECIAL_CASE_HEAP_HEADER"
+    return AGESA_FATAL;
+  }
+  LibAmdMemCopy ((VOID *) AllocHeapParams.BufferPtr, (VOID *) SpecialHeapHeader, (sizeof (S3_SPECIAL_CASE_HEAP_HEADER) * DieCount), StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the PCI device register list according to the register
+ *      list ID.
+ *
+ *      @param[in]       *Device - pointer to the PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetPCI
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3PciBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetPCI
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3PciBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AmdMemS3NBHandle" in heap for S3GetPCI
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (PCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the conditional PCI device register list according
+ *      to the register list ID.
+ *
+ *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetCPCI
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3CPciBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetCPCI
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3CPciBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AmdMemS3NBHandle" in heap for S3GetCPCI
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (CPCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the MSR device register list according to the register
+ *      list ID.
+ *
+ *      @param[in]       *Device - pointer to the MSR_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetMsr
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3MsrBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetMsr
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3MsrBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (MSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the conditional MSR device register list according
+ *      to the register list ID.
+ *
+ *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER            **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                     *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetCMsr
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetCMsr
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AmdMemS3NBHandle" in heap for S3GetCMsr
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initialize needed data structures for S3 resume.
+ *
+ *      @param[in, out]  **S3NBPtr - Pointer to the pointer of northbridge block.
+ *      @param[in, out]  *MemPtr - Pointer to MEM_DATA_STRUCT.
+ *      @param[in, out]  *mmData - Pointer to MEM_MAIN_DATA_BLOCK.
+ *      @param[in]       *StdHeader - Config handle for library and services.
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3InitNB (
+  IN OUT   S3_MEM_NB_BLOCK **S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT **MemPtr,
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 i;
+  AGESA_STATUS RetVal;
+  LOCATE_HEAP_PTR LocHeap;
+  MEM_NB_BLOCK *NBPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 Die;
+  UINT8 DieCount;
+  BOOLEAN SkipScan;
+
+  SkipScan = FALSE;
+  LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    *MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr;
+    SkipScan = TRUE;
+  } else {
+    AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+    AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT
+      return AGESA_FATAL;
+    }
+    *MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
+  }
+  LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  mmData->MemPtr = *MemPtr;
+
+  if (!SkipScan) {
+    RetVal = MemSocketScan (mmData);
+    if (RetVal == AGESA_FATAL) {
+      return RetVal;
+    }
+  } else {
+    // We already have initialize data block, no need to do it again.
+    mmData->DieCount = mmData->MemPtr->DieCount;
+  }
+  DieCount = mmData->DieCount;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  // Search for AMD_MEM_AUTO_HANDLE on the heap first.
+  // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    *S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK)));
+    AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK"
+      return AGESA_FATAL;
+    }
+    *S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+
+    LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+    if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+      // NB block has already been constructed by main block.
+      // No need to construct it here.
+      NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    } else {
+      AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
+      AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+      AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+      if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+        ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK"
+        return AGESA_FATAL;
+      }
+      NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+    }
+    // Construct each die.
+    for (Die = 0; Die < DieCount; Die ++) {
+      i = 0;
+      ((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die];
+      while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) {
+        if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) {
+          break;
+        }
+        i++;
+      };
+      if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
+        ASSERT(FALSE); // S3 resume NB constructor not found
+        return AGESA_FATAL;
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Waits specified number of 10ns cycles
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Count - Number of 10ns cycles to wait
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemFS3Wait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  Count *= 16;
+  Count += SMsr.lo;
+  if (Count >= SMsr.lo) {
+    while (SMsr.lo < Count) {
+      LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+  } else {
+    while ((INT32) (SMsr.lo) < (INT32)Count) {
+      LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c
new file mode 100755
index 0000000000..ef1326aacc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c
@@ -0,0 +1,319 @@
+/**
+ * @file
+ *
+ * mftds.c
+ *
+ * Northbridge table drive support file for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/TABLE)
+ * @e \$Revision: 5674 $ @e \$Date: 2008-04-05 02:22:37 +0800 (Sat, 05 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mftds.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_TABLE_MFTDS_FILECODE
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MAX_BYTELANES_PER_CHANNEL   (8 + 1)  ///< Max Bytelanes per channel
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+SetTableValues (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS MTPtr
+  );
+
+VOID
+SetTableValuesLoop (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS *MTPtr,
+  IN       UINT8     time
+  );
+
+/*-----------------------------------------------------------------------------
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_TABLE_ALIAS structure
+ *     @param[in]       time     - Indicate the timing for the register which is written.
+ *
+ *     @return          None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemFInitTableDrive (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8     time
+  )
+{
+  MEM_TABLE_ALIAS *MTPtr;
+  MEM_TABLE_ALIAS *IdsMTPtr;
+
+  ASSERT (NBPtr != NULL);
+  IdsMTPtr = NULL;
+
+  MTPtr = (MEM_TABLE_ALIAS *) NBPtr->RefPtr->TableBasedAlterations;
+
+  IDS_SKIP_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)) {
+    IDS_OPTION_HOOK (IDS_INIT_DRAM_TABLE, NBPtr, &(NBPtr->MemPtr->StdHeader));
+    IDS_OPTION_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader));
+  }
+
+  SetTableValuesLoop (NBPtr, MTPtr, time);
+  SetTableValuesLoop (NBPtr, IdsMTPtr, time);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MTPtr   - Pointer to the MEM_TABLE_ALIAS structure
+ *     @param[in]       time     - Indicate the timing for the register which is written.
+ *
+ *     @return          None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+SetTableValuesLoop (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS *MTPtr,
+  IN       UINT8     time
+  )
+{
+  UINT8 i;
+  UINT8 CurDct;
+
+  if (MTPtr != NULL) {
+    CurDct = NBPtr->Dct;
+    for (i = 0; MTPtr[i].time != MTEnd; i++) {
+      if ((MTPtr[i].attr != MTAuto) && (MTPtr[i].time == time)) {
+        SetTableValues (NBPtr, MTPtr[i]);
+      }
+    }
+    NBPtr->SwitchDCT (NBPtr, CurDct);
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *   Engine for setting Table Value.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       MTPtr    - Pointer to the MEM_TABLE_ALIAS structure
+ *
+ *     @return      None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+SetTableValues (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS MTPtr
+  )
+{
+  UINT8 AccessType;
+  UINT16 ByteLane;
+  UINT8 Dct;
+  UINT8 i;
+  UINT8 j;
+  UINT32 TempVal[36];
+  UINT8 *DqsSavePtr;
+  UINT8  DqsOffset;
+  BOOLEAN SaveDqs;
+
+  AccessType = 0;
+  DqsSavePtr = NULL;
+  SaveDqs = TRUE;
+
+  ASSERT (MTPtr.time <= MTAfterMaxRdLatTrn);
+  ASSERT (MTPtr.attr <= MTAdd);
+  ASSERT (MTPtr.node <= MTNodes);
+  ASSERT (MTPtr.dct <= MTDcts);
+  ASSERT (MTPtr.dimm <= MTDIMMs);
+  ASSERT (MTPtr.data.s.bytelane <= MTBLs);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    if ((MTPtr.dct == MTDcts) || (MTPtr.dct == Dct)) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      switch (MTPtr.bfindex) {
+      case BFRcvEnDly:
+        AccessType = AccessRcvEnDly;
+        DqsSavePtr = NULL;
+        break;
+      case BFWrDatDly:
+        AccessType = AccessWrDatDly;
+        DqsSavePtr = NBPtr->ChannelPtr->WrDatDlys;
+        break;
+      case BFRdDqsDly:
+        AccessType = AccessRdDqsDly;
+        DqsSavePtr = NBPtr->ChannelPtr->RdDqsDlys;
+        break;
+      case BFWrDqsDly:
+        AccessType = AccessWrDqsDly;
+        DqsSavePtr = NBPtr->ChannelPtr->WrDqsDlys;
+        break;
+      case BFPhRecDly:
+        AccessType = AccessPhRecDly;
+        SaveDqs = FALSE;
+        break;
+      default:
+        AccessType = 0xFF;
+        break;
+      }
+      if (AccessType == 0xFF) {
+        if (MTPtr.attr == MTOverride) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, MTPtr.data.s.value);
+        }
+        if (MTPtr.attr == MTSubtract) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) - MTPtr.data.s.value);
+        }
+        if (MTPtr.attr == MTAdd) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) + MTPtr.data.s.value);
+        }
+      } else {
+        // Store the DQS data first
+        for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+          for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+            TempVal[i * MAX_BYTELANES_PER_CHANNEL + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j));
+          }
+        }
+        //
+        // Single Value with Bytleane mask option
+        //   Indicated by the vtype flag
+        //
+        if (MTPtr.vtype == VT_MSK_VALUE) {
+          // set the value which defined in Memory table.
+          ByteLane = MTPtr.data.s.bytelane;
+          for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+            if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) {
+              for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+                DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j);
+                if ((ByteLane & (UINT16)1) != 0) {
+                  if (MTPtr.attr == MTOverride) {
+                    TempVal[DqsOffset] = (UINT16)MTPtr.data.s.value;
+                  }
+                  if (MTPtr.attr == MTSubtract) {
+                    TempVal[DqsOffset] -= (UINT16)MTPtr.data.s.value;
+                  }
+                  if (MTPtr.attr == MTAdd) {
+                    TempVal[DqsOffset] += (UINT16)MTPtr.data.s.value;
+                  }
+                  NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]);
+                  if (SaveDqs) {
+                    if (DqsSavePtr == NULL) {
+                      NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
+                    } else {
+                      DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
+                    }
+                  }
+                }
+                ByteLane = ByteLane >> (UINT16)1;
+              }
+            }
+          }
+        } else {
+          // Multiple values specified in a byte array
+          for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+            if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) {
+              for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+                DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j);
+                if (MTPtr.attr == MTOverride) {
+                  TempVal[DqsOffset] = MTPtr.data.bytelanevalue[j];
+                }
+                if (MTPtr.attr == MTSubtract) {
+                  TempVal[DqsOffset] -= MTPtr.data.bytelanevalue[j];
+                }
+                if (MTPtr.attr == MTAdd) {
+                  TempVal[DqsOffset] += MTPtr.data.bytelanevalue[j];
+                }
+                NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]);
+                if (SaveDqs) {
+                  if (DqsSavePtr == NULL) {
+                    NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
+                  } else {
+                    DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
+                  }
+                }
+              }
+            }
+          }
+        }
+        // set the DQS value to left DIMMs.
+        i = MTPtr.dimm;
+        while ((i != MTDIMMs) && ((++i) < MAX_DIMMS_PER_CHANNEL)) {
+          for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+            NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[i * MAX_BYTELANES_PER_CHANNEL + j]);
+          }
+        }
+      }
+    }
+  }
+}
+
+
+
+
+
+