Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

20 files changed, 4446 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c
new file mode 100755
index 0000000000..582bc6ac14
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c
@@ -0,0 +1,255 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "AdvancedApi.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "CommonInits.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+EXECUTION_CACHE_REGION InitExeCacheMap[] =
+{
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitEarly stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AmdEarlyPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by the wrapper to initialize the input
+ * structure for the AllocateExecutionCache.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   AmdExeAddrMapPtr  Our Service interface struct
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AllocateExecutionCacheInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  UINT8 i;
+  ASSERT (AmdExeAddrMapPtr != NULL);
+
+  for (i = 0; i < MAX_CACHE_REGIONS; ++i) {
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr;
+    AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Initializer routine that will be invoked by the wrapper to initialize the input
+ *  structure for the AmdInitEarly.
+ *
+ *  @param[in]      StdHeader       AMD standard header config param.
+ *  @param[in,out]  EarlyParams     The service interface struct to initialize.
+ *
+ *  @retval         AGESA_SUCCESS   Always succeeds.
+ */
+AGESA_STATUS
+AmdInitEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (EarlyParams != NULL);
+
+  EarlyParams->StdHeader = *StdHeader;
+
+  // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED.
+  //
+
+  AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
+
+  AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig);
+
+  AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform initialization services required at the Early Init POST time point.
+ *
+ * Execution Cache, HyperTransport, and AP Init advanced services are performed.
+ *
+ * @param[in]     EarlyParams  The interface struct for all early services
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.
+ *
+ */
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  )
+{
+  AGESA_STATUS  CalledAgesaStatus;
+  AGESA_STATUS  EarlyInitStatus;
+  WARM_RESET_REQUEST Request;
+
+  AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
+  ASSERT (EarlyParams != NULL);
+  EarlyInitStatus = AGESA_SUCCESS;
+
+  GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+  Request.RequestBit = FALSE;
+  SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+
+  IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader);
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // Full Hypertransport Initialization
+  // IMPORTANT: All AP cores call Ht Init.  HT Init handles full init for the BSC, and map init for APs.
+  CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // AP launch
+  CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // Warm Rest, should be at the end of AmdInitEarly
+  GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+  if (Request.RequestBit == TRUE) {
+    Request.RequestBit = FALSE;
+    Request.StateBits = WR_STATE_EARLY;
+    SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+    AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader);
+  } else {
+    if (Request.StateBits < WR_STATE_EARLY) {
+      Request.StateBits = WR_STATE_EARLY;
+      SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+    }
+  }
+
+  CalledAgesaStatus = GnbInitAtEarly (
+                        &EarlyParams->StdHeader,
+                        &EarlyParams->PlatformConfig,
+                        &EarlyParams->GnbConfig
+                        );
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader);
+
+  IDS_OPTION_HOOK (IDS_AFTER_WARM_RESET, EarlyParams, &EarlyParams->StdHeader);
+  IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader);
+  return  EarlyInitStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
new file mode 100755
index 0000000000..0b58c60498
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuEnvInit.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "GnbInterface.h"
+#include "CommonInits.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITENV_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitEnv
+ *
+ *  @param[in,out]  EnvParamsPtr   Newly created interface parameters for AmdInitEnv
+ *
+ *  @retval         AGESA_SUCCESS  Always succeeds
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitEnvInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_ENV_PARAMS    *EnvParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (EnvParamsPtr != NULL);
+
+  EnvParamsPtr->StdHeader = *StdHeader;
+
+  CommonPlatformConfigInit (&EnvParamsPtr->PlatformConfig, &EnvParamsPtr->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_ENV function.
+ *
+ * This entry point is responsible for copying the heap contents from the
+ * temp RAM area to main memory.
+ *
+ * @param[in,out] EnvParams         Required input parameters for the AMD_INIT_ENV
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD env calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS  *EnvParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitEnvStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);
+
+  ASSERT (EnvParams != NULL);
+  AmdInitEnvStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));
+
+  //Copy Temp Ram heap content to Main Ram
+  AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+  EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+
+  AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+
+  AgesaStatus = GnbInitAtEnv (&EnvParams->StdHeader);
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
+  return  AmdInitEnvStatus;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
new file mode 100755
index 0000000000..aedd8964f7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
@@ -0,0 +1,269 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionDmi.h"
+#include "OptionSlit.h"
+#include "cpuLateInit.h"
+#include "cpuFeatures.h"
+#include "CommonInits.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITLATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_DMI_CONFIGURATION    OptionDmiConfiguration;  // global user config record
+extern OPTION_SLIT_CONFIGURATION   OptionSlitConfiguration; // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitLate stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AmdLatePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitLateInitializer
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitLate
+ *
+ *  @param[in, out]    IN OUT   AMD_LATE_PARAMS *LateParamsPtr
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitLateInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_LATE_PARAMS   *LateParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (LateParamsPtr != NULL);
+
+  LateParamsPtr->StdHeader = *StdHeader;
+
+  AmdLatePlatformConfigInit (&LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader);
+
+  LateParamsPtr->AcpiSlit = NULL;
+
+  LateParamsPtr->AcpiSrat = NULL;
+
+  LateParamsPtr->AcpiWheaMce = NULL;
+  LateParamsPtr->AcpiWheaCmc = NULL;
+
+  LateParamsPtr->AcpiPState = NULL;
+
+  LateParamsPtr->DmiTable = NULL;
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitLateDestructor
+ *
+ *  Destruct routine that provide a chance if something need to be done
+ *  before the end of AmdInitLate.
+ *
+ *  @param[in]    StdHeader       The standard header.
+ *  @param[in]    LateParamsPtr   AMD init late param.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitLateDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_LATE_PARAMS   *LateParamsPtr
+  )
+{
+
+  ASSERT (LateParamsPtr != NULL);
+
+  (*(OptionDmiConfiguration.DmiReleaseBuffer)) (StdHeader);
+  (*(OptionSlitConfiguration.SlitReleaseBuffer)) (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_LATE function.
+ *
+ * This entry point is responsible for creating any desired ACPI tables, providing
+ * information for DMI, and to prepare the processors for the operating system
+ * bootstrap load process.
+ *
+ * @param[in,out] LateParams     Required input parameters for the AMD_INIT_LATE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD late calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS *LateParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitLateStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
+
+  ASSERT (LateParams != NULL);
+  AmdInitLateStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader);
+
+  // _PSS, XPSS, _PCT, _PSD, _PPC Tables
+  if (LateParams->PlatformConfig.UserOptionPState) {
+    AgesaStatus = CreateAcpiTables (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // SRAT Table Generation
+  if (LateParams->PlatformConfig.UserOptionSrat) {
+    AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // SLIT Table Generation
+  if (LateParams->PlatformConfig.UserOptionSlit) {
+    AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // WHEA Table Generation
+  if (LateParams->PlatformConfig.UserOptionWhea) {
+    AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // DMI Table Generation
+  if (LateParams->PlatformConfig.UserOptionDmi) {
+    AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // Cpu Features
+  AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader);
+  if (AgesaStatus > AmdInitLateStatus) {
+    AmdInitLateStatus = AgesaStatus;
+  }
+
+  // It is the last function run by the AGESA CPU module and prepares the processor
+  // for the operating system bootstrap load process.
+  AgesaStatus = AmdCpuLate (&LateParams->StdHeader);
+  if (AgesaStatus > AmdInitLateStatus) {
+    AmdInitLateStatus = AgesaStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader);
+
+  IDS_OPTION_HOOK (IDS_BEFORE_OS, LateParams, &LateParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader);
+  AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader);
+  return  AmdInitLateStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
new file mode 100755
index 0000000000..88c0da5c9d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "CommonInits.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITMID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitMid
+ *
+ *  @param[in,out]  MidParamsPtr   Newly created interface parameters for AmdInitMid
+ *
+ *  @retval         AGESA_SUCCESS  Always succeeds
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitMidInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_MID_PARAMS    *MidParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (MidParamsPtr != NULL);
+
+  MidParamsPtr->StdHeader = *StdHeader;
+  CommonPlatformConfigInit (&MidParamsPtr->PlatformConfig, &MidParamsPtr->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_MID function.
+ *
+ * This entry point is responsible for performing any necessary functions needed
+ * after PCI bus enumeration and just before control is passed to the video option ROM.
+ *
+ * @param[in,out] MidParams      Required input parameters for the AMD_INIT_MID
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD mid calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS *MidParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  CalledStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  ASSERT (MidParams != NULL);
+  IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader);
+
+
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  CalledStatus = GnbInitAtMid (&MidParams->StdHeader);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader);
+
+  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader);
+
+  return AgesaStatus;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
new file mode 100755
index 0000000000..50b22c1bae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuPostInit.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "CommonInits.h"
+#include "cpuServices.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitPost stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AmdPostPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitPostInitializer
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitPost
+ *
+ *  @param[in, out]    IN OUT   AMD_POST_PARAMS *PostParamsPtr
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitPostInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_POST_PARAMS   *PostParamsPtr
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (PostParamsPtr != NULL);
+
+  PostParamsPtr->StdHeader = *StdHeader;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+  AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader);
+
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
+    PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig);
+    PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader;
+    AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader);
+    AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig);
+  }
+  return AgesaStatus;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitPostDestructor
+ *
+ *  Destruct routine that provide a chance if something need to be done
+ *  before the end of AmdInitPost.
+ *
+ *  @param[in]    StdHeader       The standard header.
+ *  @param[in]    PostParamsPtr   AMD init post param.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitPostDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_POST_PARAMS   *PostParamsPtr
+  )
+{
+
+  ASSERT (PostParamsPtr != NULL);
+
+  PostParamsPtr->StdHeader = *StdHeader;
+  PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader;
+
+  //
+  // AmdMemAuto completed. Here, release heap space which is used for memory init.
+  //
+  MemAmdFinalize (PostParamsPtr->MemConfig.MemData);
+  HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+
+  //
+  // AmdCpuPost completed.
+  //
+  FinalizeAtPost (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_POST function.
+ *
+ * This entry point is responsible for initializing all system memory,
+ * gathering important data out of the pre-memory cache storage into a
+ * temporary holding buffer in main memory. After that APs will be
+ * shutdown in preparation for the host environment to take control.
+ * Note: pre-memory stack will be disabled also.
+ *
+ * @param[in,out] PostParams     Required input parameters for the AMD_INIT_POST
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD POST calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS *PostParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitPostStatus;
+  WARM_RESET_REQUEST Request;
+
+  AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader);
+
+  IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
+
+  ASSERT (PostParams != NULL);
+  AmdInitPostStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader);
+
+  IDS_OPTION_HOOK (IDS_BEFORE_MEM_INIT, PostParams, &PostParams->StdHeader);
+
+  GetWarmResetFlag (&PostParams->StdHeader, &Request);
+  Request.RequestBit = FALSE;
+  SetWarmResetFlag (&PostParams->StdHeader, &Request);
+
+  AgesaStatus = GnbInitAtPost (
+                  &PostParams->StdHeader,
+                  &PostParams->MemConfig
+                  );
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData);
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  if (AgesaStatus != AGESA_FATAL) {
+
+    IDS_OPTION_HOOK (IDS_INIT_POST_MID, PostParams, &PostParams->StdHeader);
+
+    // Check BIST status
+    AgesaStatus = CheckBistStatus (&PostParams->StdHeader);
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+
+    //
+    // P-State data gathered, then, Relinquish APs
+    //
+    AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig);
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+
+    // Warm Reset
+    GetWarmResetFlag (&PostParams->StdHeader, &Request);
+    if (Request.RequestBit == TRUE) {
+      Request.RequestBit = FALSE;
+      Request.StateBits = WR_STATE_POST;
+      SetWarmResetFlag (&PostParams->StdHeader, &Request);
+      AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader);
+    } else {
+      if (Request.StateBits < WR_STATE_POST) {
+        Request.StateBits = WR_STATE_POST;
+        SetWarmResetFlag (&PostParams->StdHeader, &Request);
+      }
+    }
+
+    IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader);
+
+    IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
+    AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader);
+
+    // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost
+    AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader));
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+    PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
+  return  AmdInitPostStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c
new file mode 100755
index 0000000000..096efe20f9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c
@@ -0,0 +1,165 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 7359 $   @e \$Date: 2008-08-13 01:53:23 +0800 (Wed, 13 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "mm.h"
+#include "GnbInterface.h"
+#include "cpuRecovery.h"
+#include "cpuCacheInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITRECOVERY_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform initialization services required at the Early Init POST time point.
+ *
+ * Execution Cache, HyperTransport, C1e, and AP Init advanced services are performed.
+ *
+ * @param[in, out]     RecoveryParams  The interface struct for Recovery services
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.
+ *
+ */
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS      *RecoveryParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  CalledAgesaStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitRecoveryEntry, &RecoveryParams->StdHeader);
+
+  ASSERT (RecoveryParams != NULL);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&RecoveryParams->StdHeader, &RecoveryParams->CacheRegion[0]);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdHtInitRecovery (&RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdCpuRecovery ((AMD_CPU_RECOVERY_PARAMS *) &RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdMemRecovery (RecoveryParams->MemConfig.MemData);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdGnbRecovery (&RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdInitRecoveryExit, &RecoveryParams->StdHeader);
+  return  AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Initialize defaults and options for Amd Init Reset.
+ *
+ * @param[in]  StdHeader              AMD standard header config param.
+ * @param[in]  AmdRecoveryParamsPtr   The Reset Init interface to initialize.
+ *
+ * @retval     AGESA_SUCCESS    Always Succeeds.
+ */
+AGESA_STATUS
+AmdInitRecoveryInitializer (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN OUT   AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (AmdRecoveryParamsPtr != NULL);
+
+  AmdRecoveryParamsPtr->StdHeader = *StdHeader;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+  AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &AmdRecoveryParamsPtr->StdHeader) == AGESA_SUCCESS) {
+    AmdRecoveryParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
+    AmdRecoveryParamsPtr->MemConfig.MemData->ParameterListPtr = &(AmdRecoveryParamsPtr->MemConfig);
+    LibAmdMemCopy ((VOID *) AmdRecoveryParamsPtr->MemConfig.MemData,
+                   (VOID *) AmdRecoveryParamsPtr,
+                   (UINTN) sizeof (AmdRecoveryParamsPtr->StdHeader),
+                   &AmdRecoveryParamsPtr->StdHeader
+                  );
+    AmdMemInitDataStructDefRecovery (AmdRecoveryParamsPtr->MemConfig.MemData);
+    return AGESA_SUCCESS;
+  } else {
+    return AGESA_ERROR;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
new file mode 100755
index 0000000000..cc7b682b0a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
@@ -0,0 +1,207 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuServices.h"
+#include "AdvancedApi.h"
+#include "GeneralServices.h"
+#include "OptionsHt.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITRESET_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST OPTION_HT_INIT_RESET HtOptionInitReset;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+EXECUTION_CACHE_REGION InitResetExeCacheMap[] =
+{
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by the wrapper to initialize the input
+ * structure for the AllocateExecutionCache.
+ *
+ *  Parameters:
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   AmdExeAddrMapPtr  Our Service interface struct
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdInitResetExecutionCacheAllocateInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  UINT8 i;
+  ASSERT (AmdExeAddrMapPtr != NULL);
+
+  for (i = 0; i < MAX_CACHE_REGIONS; ++i) {
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitResetExeCacheMap[i].ExeCacheStartAddr;
+    AmdExeAddrMapPtr[i].ExeCacheSize = InitResetExeCacheMap[i].ExeCacheSize;
+  }
+
+  return AGESA_SUCCESS;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_RESET function.
+ *
+ * This entry point is responsible for establishing the HT links to the program
+ * ROM and for performing basic processor initialization.
+ *
+ * @param[in,out] ResetParams    Required input parameters for the AMD_INIT_RESET
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD reset calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS *ResetParams
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledAgesaStatus;
+  WARM_RESET_REQUEST Request;
+
+  AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
+  ASSERT (ResetParams != NULL);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  GetWarmResetFlag (&ResetParams->StdHeader, &Request);
+  Request.RequestBit = FALSE;
+  SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  // Initialize the PCI MMIO access mechanism
+  InitializePciMmio (&ResetParams->StdHeader);
+
+  // Initialize Hyper Transport Registers
+  if (HtOptionInitReset.HtInitReset != NULL) {
+    CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig);
+    if (CalledAgesaStatus > AgesaStatus) {
+      AgesaStatus = CalledAgesaStatus;
+    }
+  }
+
+  // Warm Rest, should be at the end of AmdInitReset
+  GetWarmResetFlag (&ResetParams->StdHeader, &Request);
+  if (Request.RequestBit == TRUE) {
+    Request.RequestBit = FALSE;
+    Request.StateBits = WR_STATE_RESET;
+    SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+    AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader);
+  } else {
+    if (Request.StateBits < WR_STATE_RESET) {
+      Request.StateBits = WR_STATE_RESET;
+      SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+    }
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader);
+
+  AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader);
+  return  AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize defaults and options for Amd Init Reset.
+ *
+ * @param[in]  StdHeader        Header
+ * @param[in]  AmdResetParams   The Reset Init interface to initialize.
+ *
+ * @retval     AGESA_SUCCESS    Always Succeeds.
+ */
+AGESA_STATUS
+AmdInitResetConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_RESET_PARAMS     *AmdResetParams
+  )
+{
+  ASSERT (AmdResetParams != NULL);
+
+  AmdResetParams->StdHeader = *StdHeader;
+
+  AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]);
+  AmdHtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig);
+
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c
new file mode 100755
index 0000000000..3c6c04a7fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c
@@ -0,0 +1,223 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "Filecode.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuPostInit.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "CommonInits.h"
+#include "cpuFeatures.h"
+#define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_RESUME function.
+ *
+ * This entry point is responsible for performing silicon device and memory
+ * re-initialization for the resume boot path.
+ *
+ * @param[in]     ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD resume calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  VOID   *OrMaskPtr;
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS AmdInitResumeStatus;
+  BSC_AP_MSR_SYNC ApMsrSync[4];
+
+  AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader);
+
+  AmdInitResumeStatus = AGESA_SUCCESS;
+
+  ASSERT (ResumeParams != NULL);
+
+  if (ResumeParams->S3DataBlock.NvStorage != NULL) {
+
+    MemS3ResumeInitNB (&ResumeParams->StdHeader);
+
+    // Restore registers before exiting self refresh
+    RestorePreESRContext (&OrMaskPtr,
+                          ResumeParams->S3DataBlock.NvStorage,
+                          INIT_RESUME,
+                          &ResumeParams->StdHeader);
+    // Exit self refresh
+    ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader);
+    if (ReturnStatus > AmdInitResumeStatus) {
+      AmdInitResumeStatus = ReturnStatus;
+    }
+    if (ReturnStatus == AGESA_SUCCESS) {
+
+      // Restore registers after exiting self refresh
+      RestorePostESRContext (OrMaskPtr,
+                             ResumeParams->S3DataBlock.NvStorage,
+                             INIT_RESUME,
+                             &ResumeParams->StdHeader);
+
+      ApMsrSync[0].RegisterAddress = SYS_CFG;
+      ApMsrSync[1].RegisterAddress = TOP_MEM;
+      ApMsrSync[2].RegisterAddress = TOP_MEM2;
+      ApMsrSync[3].RegisterAddress = 0;
+      SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader);
+
+      ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
+      if (ReturnStatus > AmdInitResumeStatus) {
+        AmdInitResumeStatus = ReturnStatus;
+      }
+    }
+  }
+
+  RelinquishControlOfAllAPs (&ResumeParams->StdHeader);
+
+  AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader);
+  return (AmdInitResumeStatus);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_INIT_RESUME function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_INIT_RESUME entry point.
+ *
+ * @param[in]     StdHeader       The standard header.
+ * @param[in,out] ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdInitResumeInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (ResumeParams != NULL);
+
+  ResumeParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&ResumeParams->S3DataBlock);
+  CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Destructor for the AMD_INIT_RESUME function.
+ *
+ * This routine is responsible for deallocation of heap space allocated during
+ * AMD_INIT_RESUME entry point.
+ *
+ * @param[in]    StdHeader       The standard header.
+ * @param[in,out] ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+AmdInitResumeDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS RetVal;
+
+  ASSERT (ResumeParams != NULL);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  // Deallocate heap space allocated during memory S3 resume
+  RetVal = MemS3Deallocate (&ResumeParams->StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  return ReturnStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
new file mode 100755
index 0000000000..cbb0b75639
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "Options.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDLATERUNAPTASK_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST DISPATCH_TABLE ApDispatchTable[];
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Application Processor perform a function as directed by the BSC.
+ *
+ * This is needed for an AP task that must run after AGESA has relinquished control
+ * of the APs to the IBV.
+ *
+ * @param[in]     AmdApExeParams  The interface struct for any required routine.
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.  Note
+ *                that this will be the return value passed back to the BSC as the
+ *                return value for the call out.
+ *
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  )
+{
+  AGESA_STATUS        CalledAgesaStatus;
+  AGESA_STATUS        ApLateTaskStatus;
+  DISPATCH_TABLE      *Entry;
+
+  AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader);
+
+  ASSERT (AmdApExeParams != NULL);
+  ApLateTaskStatus = AGESA_SUCCESS;
+  CalledAgesaStatus = AGESA_UNSUPPORTED;
+
+  // Dispatch, if valid
+  Entry = (DISPATCH_TABLE *) ApDispatchTable;
+  while (Entry->FunctionId != 0) {
+    if (AmdApExeParams->FunctionNumber == Entry->FunctionId) {
+      CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams);
+      break;
+    }
+    Entry++;
+  }
+
+  if (CalledAgesaStatus > ApLateTaskStatus) {
+    ApLateTaskStatus = CalledAgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader);
+  return  ApLateTaskStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_LATE_RUN_AP_TASK function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3_SAVE entry point.
+ *
+ * @param[in]     StdHeader      The standard header.
+ * @param[in,out] AmdApExeParams Required input parameters for the AMD_LATE_RUN_AP_TASK
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdLateRunApTaskInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AP_EXE_PARAMS     *AmdApExeParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (AmdApExeParams != NULL);
+
+  AmdApExeParams->StdHeader = *StdHeader;
+  AmdApExeParams->FunctionNumber = 0;
+  AmdApExeParams->RelatedDataBlock = NULL;
+  AmdApExeParams->RelatedBlockLength = 0;
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c
new file mode 100755
index 0000000000..5cdf954d2c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c
@@ -0,0 +1,207 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "S3.h"
+#include "cpuFeatures.h"
+#include "S3SaveState.h"
+#include "CommonInits.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDS3LATERESTORE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdS3LateRestorePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_S3LATE_RESTORE function.
+ *
+ * This entry point is responsible for restoring saved registers and preparing the
+ * silicon components for OS restart.
+ *
+ * @param[in,out] S3LateParams   Required input parameters for the AMD_S3LATE_RESTORE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD S3 late restore calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  )
+{
+  UINT8  *BufferPointer;
+  VOID   *OrMaskPtr;
+  VOID   *LateContextPtr;
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS CalledStatus;
+
+  AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  ASSERT (S3LateParams != NULL);
+
+  BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
+  S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
+  ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
+
+  IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));
+
+  if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {
+    LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];
+    // Restore registers before exiting self refresh
+    RestorePreESRContext (&OrMaskPtr,
+                          LateContextPtr,
+                          S3_LATE_RESTORE,
+                          &S3LateParams->StdHeader);
+    // Restore registers after exiting self refresh
+    RestorePostESRContext (OrMaskPtr,
+                           LateContextPtr,
+                           S3_LATE_RESTORE,
+                           &S3LateParams->StdHeader);
+  }
+
+  // Dispatch any features needing to run at this time point
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,
+                                      &S3LateParams->PlatformConfig,
+                                      &S3LateParams->StdHeader);
+  if (CalledStatus > ReturnStatus) {
+    ReturnStatus = CalledStatus;
+  }
+
+  CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);
+  if (CalledStatus > ReturnStatus) {
+    ReturnStatus = CalledStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);
+  return  ReturnStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3LATE_RESTORE function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3LATE_RESTORE entry point.
+ *
+ * @param[in]     StdHeader         AMD standard header config param.
+ * @param[in,out] S3LateParams      Required input parameters for the
+ *                                  AMD_S3LATE_RESTORE entry point.
+ *
+ * @retval        AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestoreInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (S3LateParams != NULL);
+
+  S3LateParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&S3LateParams->S3DataBlock);
+
+  AmdS3LateRestorePlatformConfigInit (&S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdS3Save stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval          AGESA_SUCCESS    Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestorePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c
new file mode 100755
index 0000000000..4458d20a53
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c
@@ -0,0 +1,370 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "CommonInits.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Topology.h"
+#define FILECODE PROC_COMMON_AMDS3SAVE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST UINT32 ROMDATA S3LateHeapTable[] =
+{
+  EVENT_LOG_BUFFER_HANDLE,
+  SOCKET_DIE_MAP_HANDLE,
+  NODE_ID_MAP_HANDLE,
+  LOCAL_AP_MAIL_BOX_CACHE_HANDLE,
+  IDS_CONTROL_HANDLE,
+  AMD_S3_SCRIPT_SAVE_TABLE_HANDLE
+};
+
+#define S3LATE_TABLE_SIZE (sizeof (S3LateHeapTable) / sizeof (UINT32)) //(sizeof (S3LateHeapTable) / sizeof (S3LATE_HEAP_ELEMENT))
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdS3SavePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_S3_SAVE function.
+ *
+ * This entry point is responsible for saving silicon component registers to the
+ * SMM save area in preparation of entering system suspend-to-RAM mode.
+ *
+ * @param[in,out] AmdS3SaveParams   Required input parameters for the AMD_S3_SAVE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD S3 save calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS *AmdS3SaveParams
+  )
+{
+  UINTN  i;
+  UINT32 EarlyBufferSize;
+  UINT32 LateBufferSize;
+  UINT32 LateContextSize;
+  UINT32 HeapSize;
+  UINT8  *BufferPointer;
+  UINT8  HeapStatus;
+  ALLOCATE_HEAP_PARAMS HeapParams;
+  AGESA_BUFFER_PARAMS AllocParams;
+  DEVICE_BLOCK_HEADER *MemoryRelatedDeviceList;
+  DEVICE_BLOCK_HEADER *NonMemoryRelatedDeviceList;
+  AGESA_STATUS ReturnStatus;
+  VOID   *HeapPtrs[S3LATE_TABLE_SIZE];
+  UINT32 HeapSizes[S3LATE_TABLE_SIZE];
+  UINT32 HeapBuffersPresent;
+  HEAP_MANAGER *HeapPtr;
+
+  AGESA_TESTPOINT (TpIfAmdS3SaveEntry, &AmdS3SaveParams->StdHeader);
+
+  ASSERT (AmdS3SaveParams != NULL);
+
+  HeapBuffersPresent = 0;
+  EarlyBufferSize = 0;
+  LateBufferSize = 0;
+  LateContextSize = 0;
+  HeapSize = 0;
+  NonMemoryRelatedDeviceList = NULL;
+  ReturnStatus = AGESA_SUCCESS;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SAVE, AmdS3SaveParams, &(AmdS3SaveParams->StdHeader)) {
+
+    // Get memory device list
+    MemFS3GetDeviceList (&MemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
+    if (MemoryRelatedDeviceList != NULL) {
+      // Determine size needed
+      EarlyBufferSize = GetWorstCaseContextSize (MemoryRelatedDeviceList, INIT_RESUME, &AmdS3SaveParams->StdHeader);
+    }
+
+    if (UserOptions.CfgS3LateRestore) {
+      AllocParams.StdHeader = AmdS3SaveParams->StdHeader;
+      for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
+        AllocParams.BufferHandle = S3LateHeapTable[i];
+        AllocParams.BufferLength = 0;
+        if (AgesaLocateBuffer (0, &AllocParams) == AGESA_SUCCESS) {
+          ASSERT (AllocParams.BufferLength != 0);
+          HeapBuffersPresent++;
+          HeapSize += AllocParams.BufferLength; //S3LateHeapTable[i].BufferLength;
+          HeapPtrs[i] = AllocParams.BufferPointer;
+          HeapSizes[i] = AllocParams.BufferLength;
+        } else {
+          HeapPtrs[i] = NULL;
+          HeapSizes[i] = 0;
+        }
+      }
+
+      // Determine heap data size requirements
+      if (HeapBuffersPresent != 0) {
+        HeapSize += (((sizeof (HEAP_MANAGER)) + (HeapBuffersPresent * (sizeof (BUFFER_NODE)))) + (HeapBuffersPresent * (2 * SIZE_OF_SENTINEL)));
+      }
+
+      // Get non memory device list
+      GetNonMemoryRelatedDeviceList (&NonMemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
+
+      if (NonMemoryRelatedDeviceList != NULL) {
+        // Determine size needed
+        LateContextSize = GetWorstCaseContextSize (NonMemoryRelatedDeviceList, S3_LATE_RESTORE, &AmdS3SaveParams->StdHeader);
+      }
+      LateBufferSize = HeapSize + LateContextSize;
+      if (LateBufferSize != 0) {
+        LateBufferSize += sizeof (S3_VOLATILE_STORAGE_HEADER);
+      }
+    }
+
+    if ((EarlyBufferSize != 0) || (LateBufferSize != 0)) {
+      //
+      // Allocate a buffer by callback function
+      //
+      AllocParams.StdHeader = AmdS3SaveParams->StdHeader;
+      AllocParams.BufferLength = EarlyBufferSize + LateBufferSize;
+      AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE;
+
+      AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
+      if (AgesaAllocateBuffer (0, &AllocParams) != AGESA_SUCCESS) {
+        if (AGESA_ERROR > ReturnStatus) {
+          ReturnStatus = AGESA_ERROR;
+        }
+      }
+      AGESA_TESTPOINT (TpIfAfterAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
+
+      if (EarlyBufferSize != 0) {
+        AmdS3SaveParams->S3DataBlock.NvStorage = AllocParams.BufferPointer;
+        SaveDeviceListContext (MemoryRelatedDeviceList,
+                           AmdS3SaveParams->S3DataBlock.NvStorage,
+                           INIT_RESUME,
+                           &EarlyBufferSize,
+                           &AmdS3SaveParams->StdHeader);
+
+        AmdS3SaveParams->S3DataBlock.NvStorageSize = EarlyBufferSize;
+      }
+
+      if (LateBufferSize != 0) {
+        BufferPointer = AllocParams.BufferPointer;
+        AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]);
+
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = 0;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = 0;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize;
+
+        if (HeapSize != 0) {
+          // Transfer heap contents
+          ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = sizeof (S3_VOLATILE_STORAGE_HEADER);
+          HeapPtr = (HEAP_MANAGER *) &BufferPointer[EarlyBufferSize + sizeof (S3_VOLATILE_STORAGE_HEADER)];
+          HeapPtr->AvailableSize = (UINT16) (HeapSize - sizeof (HEAP_MANAGER));
+
+          HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus;
+          AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+          AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT32) HeapPtr;
+
+          for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
+            if (HeapPtrs[i] != NULL) {
+              HeapParams.RequestedBufferSize = (UINT16) HeapSizes[i]; // S3LateHeapTable[i].BufferLength;
+              HeapParams.BufferHandle = S3LateHeapTable[i];
+              HeapParams.Persist = HEAP_S3_RESUME;
+              if (HeapAllocateBuffer (&HeapParams, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) {
+                LibAmdMemCopy ((VOID *) HeapParams.BufferPtr, HeapPtrs[i], HeapSizes[i], &AmdS3SaveParams->StdHeader);
+              }
+            }
+          }
+
+          AmdS3SaveParams->StdHeader.HeapStatus = HeapStatus;
+        }
+
+
+        if (LateContextSize != 0) {
+
+          ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
+
+          SaveDeviceListContext (NonMemoryRelatedDeviceList,
+                                &(BufferPointer[EarlyBufferSize + HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]),
+                                S3_LATE_RESTORE,
+                                &LateContextSize,
+                                &AmdS3SaveParams->StdHeader);
+        }
+
+        AmdS3SaveParams->S3DataBlock.VolatileStorageSize = HeapSize + LateContextSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
+      }
+    }
+  }
+  IDS_OPTION_HOOK (IDS_AFTER_S3_SAVE, AmdS3SaveParams, &AmdS3SaveParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdS3SaveExit, &AmdS3SaveParams->StdHeader);
+  return  ReturnStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3_SAVE function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3_SAVE entry point.
+ *
+ * @param[in]    StdHeader       The standard header.
+ * @param[in,out] S3SaveParams   Required input parameters for the AMD_S3_SAVE
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3SaveInitializer (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (S3SaveParams != NULL);
+
+  S3SaveParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&S3SaveParams->S3DataBlock);
+
+  AmdS3SavePlatformConfigInit (&S3SaveParams->PlatformConfig, &S3SaveParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Destructor for the AMD_S3_SAVE function.
+ *
+ * This routine is responsible for deallocation of heap space allocated during
+ * AMD_S3_SAVE entry point.
+ *
+ * @param[in]     StdHeader       The standard header.
+ * @param[in,out] S3SaveParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+AmdS3SaveDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  )
+{
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS RetVal;
+
+  ASSERT (S3SaveParams != NULL);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  // Deallocate heap space allocated during memory S3 save
+  RetVal = MemS3Deallocate (&S3SaveParams->StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  RetVal = HeapDeallocateBuffer (AMD_S3_NB_INFO_BUFFER_HANDLE, StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  RetVal = HeapDeallocateBuffer (AMD_S3_INFO_BUFFER_HANDLE, StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  return ReturnStatus;
+}
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdS3Save stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval          AGESA_SUCCESS    Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3SavePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
new file mode 100755
index 0000000000..17726cb27e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
@@ -0,0 +1,114 @@
+/**
+ * @file
+ *
+ * Common initialization routines.
+ *
+ * Contains common initialization routines across AGESA entries of phases.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "CommonInits.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_COMMONINITS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------------*/
+
+/**
+ * Common routine to initialize PLATFORM_CONFIGURATION.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+CommonPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile;
+  PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList;
+  PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode;
+  PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode;
+  PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData;
+  PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode;
+  PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData;
+  PlatformConfig->UserOptionDmi = UserOptions.OptionDmi;
+  PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates;
+  PlatformConfig->UserOptionSrat = UserOptions.OptionSrat;
+  PlatformConfig->UserOptionSlit = UserOptions.OptionSlit;
+  PlatformConfig->UserOptionWhea = UserOptions.OptionWhea;
+  PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue;
+  PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent;
+  PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics;
+  PlatformConfig->VrmProperties = UserOptions.CfgPlatVrmCfg;
+  PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb;
+  PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0;
+  PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1;
+
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h
new file mode 100755
index 0000000000..93a9304e70
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h
@@ -0,0 +1,65 @@
+/**
+ * @file
+ *
+ * Common initialization routines.
+ *
+ * Contains common initialization routines across AGESA entries of phases.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _COMMON_INITS_H_
+#define _COMMON_INITS_H_
+
+/**
+ * Common routine to initialize PLATFORM_CONFIGURATION.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+CommonPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+#endif // _COMMON_INITS_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonPage.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonPage.h
new file mode 100755
index 0000000000..c16af47566
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonPage.h
@@ -0,0 +1,116 @@
+/**
+ * @file
+ *
+ * Create outline and references for Processor Common Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page commonmain Processor Common Component Documentation
+ *
+ * Additional documentation for the Common component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage amdconfigparamname "Naming Guidelines for type AMD_CONFIG_PARAMS"
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
+
+/**
+ * @page amdconfigparamname Naming Guidelines for type AMD_CONFIG_PARAMS
+ * @par
+ * These are the guidelines for naming objects of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * in AGESA code.
+ * <ul>
+ *
+ * <li>
+ * Formal parameter names of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * will always be named
+ * StdHeader. This covers all function prototypes, function definitions, and method typedefs (a
+ * typedef of a function prototype) in AGESA code. Examples:
+ * @n @code
+ * VOID
+ *   LibAmdPciFindNextCap (
+ *     IN OUT   PCI_ADDR *Address,
+ *     IN       AMD_CONFIG_PARAMS *StdHeader
+ *     )
+ *
+ * typedef VOID F_DO_TABLE_ENTRY (
+ *   IN       TABLE_ENTRY_DATA       *CurrentEntry,
+ *   IN       PLATFORM_CONFIGURATION *PlatformConfig,
+ *   IN       AMD_CONFIG_PARAMS      *StdHeader
+ *   );
+ *
+ * @endcode
+ *
+ * <li>
+ * Structure members of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * will always be named StdHeader. Examples:
+ * @n @code
+   /// Example of struct member naming.
+ * typedef struct {
+ *   IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard Header
+ *   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+ * } AMD_CPU_RECOVERY_PARAMS;
+ *
+ * @endcode
+ *
+ * <li>
+ * Routines which define local variables of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * should
+ * name the local variable as closely as practical to StdHeader, but otherwise freedom is allowed. Example:
+ * @n @code
+ * AMD_CONFIG_PARAMS *NewStdHeader;
+ * [...]
+ * NewStdHeader = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+ * @endcode
+ *
+ * <li>
+ * Arguments to routines with AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * formal parameters are not
+ * checked.  Freedom is allowed in order to conform to these guidelines in a practical, readable
+ * way.  This includes typecast arguments.  Examples:
+ * @n @code
+ * Status = GetEventLog (&LogEvent, (AMD_CONFIG_PARAMS *)Event);
+ *
+ * MemS3ExitSelfRefRegDA (NBPtr, &MemPtr->StdHeader);
+ * @endcode
+ *
+ * </ul>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c
new file mode 100755
index 0000000000..f395dc1916
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_COMMONRETURNS_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return False.
+*
+* @retval FALSE  Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse (VOID)
+{
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 (VOID)
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 (VOID)
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 (VOID)
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL (VOID)
+{
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess (VOID)
+{
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid (VOID)
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert (VOID)
+{
+  ASSERT (FALSE);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c
new file mode 100755
index 0000000000..990a10c1c0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c
@@ -0,0 +1,291 @@
+/**
+ * @file
+ *
+ * AMD AGESA Input Structure Creation
+ *
+ * Contains AGESA input structure creation support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 6913 $   @e \$Date: 2008-07-23 11:34:49 -0500 (Wed, 23 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_CREATESTRUCT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST FUNCTION_PARAMS_INFO FuncParamsInfo[];
+extern CONST UINTN InitializerCount;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocate and initialize Config headers and Service Interface structures.
+ *
+ * This function will be called for each AGESA public APIs.
+ * This function will do the following:
+ * -# Locate the AGESA API structure parameters initializer function information.
+ * -# Find the size of the structure that gets passed to each public APIs as
+ *    the entry parameter. Allocate heap space using the size for PreMemHeap, callout for
+ *    memory allocation for PostMemDram, and just set the config and service interface
+ *    pointers for ByHost.
+ * -# If the allocation is not ByHost, copy the AmdConfigParams into the newly created AmdConfigParams.
+ *    For ByHost, we're using the caller's existing config params.
+ * -# Call the initializer function, and pass a reference to the Config params and to
+ *    the Service Interface struct.  On return the constructor will have filled the
+ *    remaining structure with default values.
+ * -# Fill the remaining info in the newly created structure on heap in AMD_CONFIG_PARAMS
+ *    area (i.e. Fill *newStructPtr with the pointer to the newly created structure)
+ * -# Set the appropriate AGESA function number in the StdHeader member of the input
+ *    parameter structure.
+ *
+ * @param[in,out]  InterfaceParams         Pointer to structure containing the function call
+ *                                         whose parameter structure is to be created, the
+ *                                         allocation method, and a pointer to the newly
+ *                                         created structure.
+ *
+ * @retval         AGESA_SUCCESS           The interface struct is allocated and initialized.
+ * @retval         AGESA_UNSUPPORTED       The Service is not supported.
+ *
+ */
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  )
+{
+  UINTN                     ServiceIndex;
+  ALLOCATE_HEAP_PARAMS      AllocHeapParams;
+  AMD_CONFIG_PARAMS         *NewlyCreatedConfig;
+  VOID                      *NewlyCreatedServiceInterface;
+  AGESA_STATUS              AgesaStatus;
+  AGESA_STATUS              TempStatus;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  ASSERT (InterfaceParams != NULL);
+
+  switch (InterfaceParams->AgesaFunctionName) {
+  case AMD_INIT_RESET:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET;
+    AgesaStatus = HeapManagerInit (&InterfaceParams->StdHeader);
+    break;
+  case AMD_INIT_EARLY:
+  case AMD_INIT_RECOVERY:
+  case AMD_INIT_RESUME:
+  case AMD_INIT_POST:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  case AMD_INIT_ENV:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+    break;
+  case AMD_INIT_LATE:
+  case AMD_INIT_MID:
+  case AMD_S3_SAVE:
+  case AMD_LATE_RUN_AP_TASK:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_S3LATE_RESTORE:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+    break;
+  default:
+    ASSERT (FALSE);
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  }
+
+  // Step 1
+  for (ServiceIndex = 0; ServiceIndex < InitializerCount; ServiceIndex++) {
+    if (FuncParamsInfo[ServiceIndex].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
+      break;
+    }
+  }
+  if (ServiceIndex >= InitializerCount) {
+    // A call was made to AGESA with an invalid function number.  This wrapper error may be due to the build target
+    // not containing the desired entry point.
+    return AGESA_UNSUPPORTED;
+  }
+
+  // Step 2
+  LibAmdMemFill (&AllocHeapParams, 0, (UINTN) (sizeof (ALLOCATE_HEAP_PARAMS)), &InterfaceParams->StdHeader);
+
+  if (InterfaceParams->AllocationMethod < ByHost) {
+    // Allocate one buffer to contain the config params and the service struct.
+    // The service struct begins immediately after the config params.
+    AllocHeapParams.RequestedBufferSize = FuncParamsInfo[ServiceIndex].CreateStructSize + sizeof (AMD_CONFIG_PARAMS);
+    AllocHeapParams.BufferHandle = FuncParamsInfo[ServiceIndex].BufferHandle;
+    TempStatus = HeapAllocateBuffer (&AllocHeapParams, &(InterfaceParams->StdHeader));
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+    NewlyCreatedConfig++;
+    NewlyCreatedServiceInterface =  NewlyCreatedConfig;
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+  } else {
+    // The caller (example, agesa basic interface implementation) already has a buffer to use.
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)InterfaceParams;
+    NewlyCreatedServiceInterface = InterfaceParams->NewStructPtr;
+    ASSERT (InterfaceParams->NewStructSize >= FuncParamsInfo[ServiceIndex].CreateStructSize);
+  }
+  ASSERT (NewlyCreatedConfig != NULL);
+  ASSERT (NewlyCreatedServiceInterface != NULL);
+
+  // Step 3
+  if (InterfaceParams->AllocationMethod != ByHost) {
+    *NewlyCreatedConfig = InterfaceParams->StdHeader;
+  }
+
+  // Step 4
+  TempStatus = FuncParamsInfo[ServiceIndex].AgesaFunction (NewlyCreatedConfig, NewlyCreatedServiceInterface);
+  AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+
+  // Step 5
+  if (InterfaceParams->AllocationMethod != ByHost) {
+    InterfaceParams->NewStructPtr = (VOID *) NewlyCreatedServiceInterface;
+    InterfaceParams->NewStructSize = FuncParamsInfo[ServiceIndex].CreateStructSize;
+  }
+
+  // Step 6
+  ((AMD_CONFIG_PARAMS *) InterfaceParams->NewStructPtr)->Func = InterfaceParams->AgesaFunctionName;
+  return AgesaStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Clears storage space from allocation for a parameter block of an
+ *  AGESA software call entry.
+ *
+ *  @param[in,out]  InterfaceParams         Pointer to structure containing the function call
+ *                                          whose parameter structure is to be deallocated.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  )
+{
+  UINT8 i;
+  UINT8 *BufferPtr;
+  VOID  *ServicePtr;
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  TempStatus;
+  LOCATE_HEAP_PTR LocHeap;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  switch (InterfaceParams->AgesaFunctionName) {
+  case AMD_INIT_RESET:
+  case AMD_INIT_EARLY:
+  case AMD_INIT_RECOVERY:
+  case AMD_INIT_RESUME:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  case AMD_INIT_POST:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+    break;
+  case AMD_INIT_ENV:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_INIT_LATE:
+  case AMD_INIT_MID:
+  case AMD_S3_SAVE:
+  case AMD_LATE_RUN_AP_TASK:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_S3LATE_RESTORE:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+    break;
+  default:
+    ASSERT (FALSE);
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  }
+
+// Step 1
+  for (i = 0; i < InitializerCount; i++) {
+    if (FuncParamsInfo[i].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
+      break;
+    }
+  }
+  if (i >= InitializerCount) {
+    return AGESA_BOUNDS_CHK;
+  }
+
+  // Step 2
+  LocHeap.BufferHandle = FuncParamsInfo[i].BufferHandle;
+  if (HeapLocateBuffer (&LocHeap, &(InterfaceParams->StdHeader)) == AGESA_SUCCESS) {
+    BufferPtr = (UINT8 *) LocHeap.BufferPtr;
+    ServicePtr = &BufferPtr[sizeof (AMD_CONFIG_PARAMS)];
+    TempStatus = FuncParamsInfo[i].AgesaDestructor (&(InterfaceParams->StdHeader), ServicePtr);
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+  }
+
+  // Step 3
+  if (InterfaceParams->AllocationMethod < ByHost) {
+    TempStatus = HeapDeallocateBuffer (FuncParamsInfo[i].BufferHandle, &(InterfaceParams->StdHeader));
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+  } else {
+    // Unless we define service specific destructors, nothing to do for ByHost.
+    return AGESA_SUCCESS;
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h
new file mode 100755
index 0000000000..b19147b0bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h
@@ -0,0 +1,195 @@
+/**
+ * @file
+ *
+ * AMD AGESA Input Structure Creation
+ *
+ * Contains AGESA input creation structures.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 6913 $   @e \$Date: 2008-07-23 11:34:49 -0500 (Wed, 23 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CREATE_STRUCT_H_
+#define _CREATE_STRUCT_H_
+
+/**
+ * A constructor method.
+ *
+ * Sets inputs to valid, basic level, defaults for the specific service instance.
+ * Constructors should avoid using the header, since these routines should not
+ * do operations which may fail or require status back to the user.  The constructor
+ * should always SUCCEED.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   ServiceInterface  Service Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+typedef AGESA_STATUS
+F_AGESA_FUNCTION (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       VOID                 *ServiceInterface
+  );
+
+/// Reference to a Method.
+typedef F_AGESA_FUNCTION *PF_AGESA_FUNCTION;
+
+/**
+ * A Destructor method.
+ *
+ * Sets inputs to valid, basic level, defaults for the specific service instance.
+ * The constructor should always SUCCEED.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header.
+ * @param[in]   ServiceInterface  Service Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+typedef AGESA_STATUS
+F_AGESA_DESTRUCTOR (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       VOID                 *ServiceInterface
+  );
+
+/// Reference to a Method.
+typedef F_AGESA_DESTRUCTOR *PF_AGESA_DESTRUCTOR;
+
+/**
+ * Provide the information needed to invoke each service constructor.
+ */
+typedef struct {
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< Identifies the service
+  IN       UINT16              CreateStructSize;   ///< The service's input struct size.
+                                                   ///  Do NOT include a config params header!
+     OUT   PF_AGESA_FUNCTION   AgesaFunction;      ///< The constructor function
+     OUT   PF_AGESA_DESTRUCTOR AgesaDestructor;    ///< The destructor function.
+  IN       AGESA_BUFFER_HANDLE BufferHandle;       ///< The buffer handle id for the service.
+} FUNCTION_PARAMS_INFO;
+
+/**
+ * All available services have their constructor info here.
+ */
+AGESA_STATUS
+AmdInitResetConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_RESET_PARAMS     *AmdResetParams
+  );
+
+AGESA_STATUS
+AmdInitRecoveryInitializer (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN OUT   AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  );
+
+AGESA_STATUS
+AmdInitPostInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_POST_PARAMS *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitPostDestructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_POST_PARAMS      *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitEnvInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_ENV_PARAMS *EnvParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitMidInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_MID_PARAMS *MidParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitLateInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_LATE_PARAMS *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitLateDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_LATE_PARAMS   *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitResumeInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  );
+
+AGESA_STATUS
+AmdInitResumeDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  );
+
+AGESA_STATUS
+AmdS3SaveInitializer (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  );
+
+AGESA_STATUS
+AmdS3SaveDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  );
+
+AGESA_STATUS
+AmdS3LateRestoreInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  );
+
+AGESA_STATUS
+AmdLateRunApTaskInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AP_EXE_PARAMS     *AmdApExeParams
+  );
+#endif // _CREATE_STRUCT_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
new file mode 100755
index 0000000000..3d98b388e4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
@@ -0,0 +1,304 @@
+/**
+ * @file
+ *
+ * S3 save/restore script
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 20539 $   @e \$Date: 2009-10-14 10:48:54 -0700 (Wed, 14 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_S3RESTORESTATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+AGESA_STATUS
+STATIC
+S3RestoreStateFromTable (
+  IN      S3_SAVE_TABLE_HEADER  *S3SaveTablePtr,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestore (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return OptionS3ScriptConfiguration.Restore (StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestoreStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestoreState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  S3_SAVE_TABLE_HEADER  *S3SaveTablePtr;
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    IDS_ERROR_TRAP;
+    return  AGESA_FATAL;
+  }
+  Status = S3RestoreStateFromTable (S3SaveTablePtr, StdHeader);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] S3SaveTablePtr     Pointer to S3 Save Table
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+STATIC
+S3RestoreStateFromTable (
+  IN      S3_SAVE_TABLE_HEADER  *S3SaveTablePtr,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  VOID                  *S3SaveTableRecordPtr;
+  PCI_ADDR              PciAddress;
+  S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER);
+  IDS_HDT_CONSOLE ("Start S3 restore\n");
+  while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) {
+    switch  (*(UINT16 *) S3SaveTableRecordPtr) {
+    case  SAVE_STATE_IO_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 IO Write %x\n", (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdIoWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_IO_READ_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 IO RMW %x\n", (UINT16) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdIoRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Mem Write %llx\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdMemWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_READ_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Mem RMW %llx\n", ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdMemRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      IDS_HDT_CONSOLE ("  S3 PCI Write %lx\n", PciAddress.AddressValue);
+
+      LibAmdPciWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      IDS_HDT_CONSOLE ("  S3 PCI RMW %lx\n", PciAddress.AddressValue);
+      LibAmdPciRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_STALL_OPCODE:
+      break;
+    case  SAVE_STATE_INFORMATION_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Info [%s]\n", (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_INFO_OP_HEADER));
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                             sizeof (S3_INFO_OP_HEADER) +
+                             ((S3_INFO_OP_HEADER*) S3SaveTableRecordPtr)->Length;
+      break;
+    case  SAVE_STATE_IO_POLL_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 IO Poll %x\n", (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdIoPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_POLL_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Mem Poll %llx\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdMemPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      IDS_HDT_CONSOLE ("  S3 PCI Poll %lx\n", PciAddress.AddressValue);
+      LibAmdPciPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    default:
+      IDS_HDT_CONSOLE (" ERROR!!! Invalid S3 restore opcode\n");
+      ASSERT (FALSE);
+      return AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (" End S3 Restore \n");
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c
new file mode 100755
index 0000000000..73dc8d2ed9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c
@@ -0,0 +1,453 @@
+/**
+ * @file
+ *
+ * S3 save/restore script
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 20539 $   @e \$Date: 2009-10-14 10:48:54 -0700 (Wed, 14 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_S3SAVESTATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInit (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return OptionS3ScriptConfiguration.Init (StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInitStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInitState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = S3_TABLE_LENGTH;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status == AGESA_SUCCESS) {
+    ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->TableLength = S3_TABLE_LENGTH;
+    ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->SaveOffset = sizeof (S3_SAVE_TABLE_HEADER);
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in]     StdHeader          Pointer to standard header
+ * @param[in,out] S3SaveTable        S3 save table header
+ */
+STATIC AGESA_STATUS
+S3SaveStateExtendTableLenth (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   S3_SAVE_TABLE_HEADER  **S3SaveTable
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+  VOID                  *TempBuffer;
+  UINT16                NewTableLength;
+  UINT16                CurrentTableLength;
+  //Allocate temporary buffer
+  NewTableLength = (*S3SaveTable)->TableLength + S3_TABLE_LENGTH_INCREMENT;
+  AllocHeapParams.RequestedBufferSize = NewTableLength;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  //Save current table length
+  CurrentTableLength = (*S3SaveTable)->TableLength;
+  //Update table length
+  (*S3SaveTable)->TableLength = NewTableLength;
+  //Copy S3 save toable to temporary location
+  LibAmdMemCopy (AllocHeapParams.BufferPtr, *S3SaveTable, CurrentTableLength, StdHeader);
+  //Save pointer to temp buffer
+  TempBuffer = AllocHeapParams.BufferPtr;
+  // Free original S3 save buffer
+  HeapDeallocateBuffer (AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, StdHeader);
+
+  AllocHeapParams.RequestedBufferSize = NewTableLength;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  LibAmdMemCopy (AllocHeapParams.BufferPtr, TempBuffer, AllocHeapParams.RequestedBufferSize, StdHeader);
+  *S3SaveTable = (S3_SAVE_TABLE_HEADER*) AllocHeapParams.BufferPtr;
+  HeapDeallocateBuffer (AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, StdHeader);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in]  StdHeader          Pointer to standard header
+ * @param[out] S3SaveTable        S3 save table header
+ */
+AGESA_STATUS
+S3ScriptGetS3SaveTable (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   S3_SAVE_TABLE_HEADER  **S3SaveTable
+  )
+{
+  AGESA_STATUS          Status;
+  LOCATE_HEAP_PTR       LocHeapParams;
+  LocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    *S3SaveTable = NULL;
+    return Status;
+  }
+  *S3SaveTable = (S3_SAVE_TABLE_HEADER *) LocHeapParams.BufferPtr;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 write opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Count              Number of register writes
+ * @param[in] Buffer             Pointer to write buffer
+ */
+AGESA_STATUS
+S3SaveStateSaveWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      UINT32              Count,
+  IN      VOID                *Buffer
+  )
+{
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_WRITE_OP_HEADER      *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_WRITE_OP_HEADER) + WidthLength * Count;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+  SaveOffsetPtr = (S3_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Count = Count;
+  SaveOffsetPtr->Address = Address;
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_WRITE_OP_HEADER),
+    Buffer,
+    WidthLength * Count,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 write opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Data               Pointer to data
+ * @param[in] DataMask           Pointer data mask
+ */
+AGESA_STATUS
+S3SaveStateSaveReadWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_READ_WRITE_OP_HEADER *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength * 2;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+
+  SaveOffsetPtr = (S3_READ_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Address = Address;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+    Data,
+    WidthLength,
+    StdHeader
+    );
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength,
+    DataMask,
+    WidthLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 poll opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Data               Pointer to data
+ * @param[in] DataMask           Pointer data mask
+ * @param[in] Delay              Time delay for poll
+ */
+AGESA_STATUS
+S3SaveStateSavePollOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask,
+  IN      UINT64              Delay
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_POLL_OP_HEADER       *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_POLL_OP_HEADER) + WidthLength * 2;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+
+  SaveOffsetPtr = (S3_POLL_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Delay = Delay;
+  SaveOffsetPtr->Address = Address;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER),
+    Data,
+    WidthLength,
+    StdHeader
+    );
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER) + WidthLength,
+    DataMask,
+    WidthLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 poll opcode
+ *
+ *
+ *
+ * @param[in] StdHeader              Pointer to standard header
+ * @param[in] OpCode                  Operation opcode
+ * @param[in] InformationLength  Info length
+ * @param[in] Information             Pointer to information
+ */
+AGESA_STATUS
+S3SaveStateSaveInfoOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT32              InformationLength,
+  IN      VOID                *Information
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_INFO_OP_HEADER       *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  OpCodeLength = sizeof (S3_INFO_OP_HEADER) + InformationLength;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+
+  SaveOffsetPtr = (S3_INFO_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Length = InformationLength;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
+    Information,
+    InformationLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.h
new file mode 100755
index 0000000000..60d0d8e743
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.h
@@ -0,0 +1,287 @@
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 20270 $   @e \$Date: 2009-10-09 10:09:20 -0700 (Fri, 09 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _S3SAVESTATE_H_
+#define _S3SAVESTATE_H_
+
+
+#define SAVE_STATE_IO_WRITE_OPCODE              0x00
+#define SAVE_STATE_IO_READ_WRITE_OPCODE         0x01
+#define SAVE_STATE_MEM_WRITE_OPCODE             0x02
+#define SAVE_STATE_MEM_READ_WRITE_OPCODE        0x03
+#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE      0x04
+#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05
+#define SAVE_STATE_STALL_OPCODE                 0x07
+#define SAVE_STATE_INFORMATION_OPCODE           0x0A
+#define SAVE_STATE_IO_POLL_OPCODE               0x0D
+#define SAVE_STATE_MEM_POLL_OPCODE              0x0E
+#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE       0x0F
+
+
+#define S3_TABLE_LENGTH             8 * 1024
+#define S3_TABLE_LENGTH_INCREMENT   1 * 1024
+
+/// S3 Save Table
+typedef struct {
+  UINT16                      TableLength;        ///< Table Length
+  UINT32                      SaveOffset;         ///< Save Location
+} S3_SAVE_TABLE_HEADER;
+
+/// S3 write operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register address
+  UINT32                      Count;              ///< Write count
+} S3_WRITE_OP_HEADER;
+
+/// S3 Read and Write Operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register Address
+} S3_READ_WRITE_OP_HEADER;
+
+/// S3 Poll operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register address
+  UINT64                      Delay;              ///< Time delay
+} S3_POLL_OP_HEADER;
+
+/// Information operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  UINT32                      Length;             ///< Length of info
+} S3_INFO_OP_HEADER;
+
+typedef AGESA_STATUS (*S3_SCRIPT_INIT) (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInit (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInitState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInitStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+typedef AGESA_STATUS (*S3_SCRIPT_RESTORE) (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestore (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestoreState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestoreStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptGetS3SaveTable (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  OUT     S3_SAVE_TABLE_HEADER  **S3SaveTable
+  );
+
+/// S3 Script Configuration
+typedef struct {
+  S3_SCRIPT_INIT              Init;               ///< Script initialization
+  S3_SCRIPT_RESTORE           Restore;            ///< Script restore
+} S3_SCRIPT_CONFIGURATION;
+
+AGESA_STATUS
+S3SaveStateSaveWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      UINT32              Count,
+  IN      VOID                *Buffer
+  );
+
+AGESA_STATUS
+S3SaveStateSaveReadWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask
+  );
+
+AGESA_STATUS
+S3SaveStateSavePollOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask,
+  IN      UINT64              Delay
+  );
+
+AGESA_STATUS
+S3SaveStateSaveInfoOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT32              InformationLength,
+  IN      VOID                *Information
+  );
+
+//PCI write
+#define S3_SAVE_PCI_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_WRITE_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    1,  \
+    DataPtr  \
+    )
+
+//PCI read modify write
+#define S3_SAVE_PCI_RMW (StdHeader, Address, Width, DataPtr, DataMaskPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    DataPtr,  \
+    DataMask  \
+    )
+
+//PCI read modify write
+#define S3_SAVE_PCI_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
+  S3SaveStateSavePollOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_POLL_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    DataPtr,  \
+    DataMask,  \
+    Delay  \
+    )
+
+//Memory/MMIO write
+#define S3_SAVE_MEM_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    1,  \
+    DataPtr  \
+    )
+
+//Memory/MMIO read modify write
+#define S3_SAVE_MEM_RMW(StdHeader, Address, Width, DataPtr, DataMaskPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    DataPtr,  \
+    DataMask  \
+    )
+
+//Memory/MMIO read modify write
+#define S3_SAVE_MEM_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
+  S3SaveStateSavePollOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_POLL_OPCODE,  \
+    Width,  \
+    Address, \
+    DataPtr,  \
+    DataMask,  \
+    Delay \
+    )
+
+// I/O write
+#define S3_SAVE_IO_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_IO_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    1,  \
+    DataPtr  \
+    )
+
+// Save information
+#define S3_SAVE_INFORMATION(StdHeader, InformationLength, Information) \
+  S3SaveStateSaveInfoOp (  \
+    StdHeader,  \
+    SAVE_STATE_INFORMATION_OPCODE,  \
+    InformationLength,  \
+    Information \
+    )
+
+// Save information string S3_SAVE_INFORMATION_STRING (StdHeader, "Message")
+#define S3_SAVE_INFORMATION_STRING(StdHeader, Information) \
+  S3SaveStateSaveInfoOp (  \
+    StdHeader,  \
+    SAVE_STATE_INFORMATION_OPCODE,  \
+    sizeof (Information),  \
+    Information \
+    )
+
+#endif