Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 101 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionCpuCacheFlushOnHaltInstall.h
new file mode 100755
index 0000000000..966624c65f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * Install of build option: CPU Cache Flush On Halt
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 17487 $   @e \$Date: 2009-08-06 14:17:58 -0500 (Thu, 06 Aug 2009) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+
+#include "cpuPostInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+#define F10_BL_CPU_CFOH_SUPPORT
+#define F10_DA_CPU_CFOH_SUPPORT
+#define F10_CPU_CFOH_SUPPORT
+
+#if OPTION_CPU_CFOH == TRUE
+  #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY10H_BL == TRUE
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
+          #undef F10_BL_CPU_CFOH_SUPPORT
+          #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
+        #endif
+
+        #if OPTION_FAMILY10H_DA == TRUE
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
+          #undef F10_DA_CPU_CFOH_SUPPORT
+          #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
+        #endif
+
+        #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE)
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
+          #undef F10_CPU_CFOH_SUPPORT
+          #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY, &F10CacheFlushOnHalt},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
+{
+  F10_BL_CPU_CFOH_SUPPORT
+  F10_DA_CPU_CFOH_SUPPORT
+  F10_CPU_CFOH_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
+{
+  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CacheFlushOnHaltFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_