AGESA boards: Split dispatcher to romstage and ramstage

The way dispatcher table is set up prevents linker from
optimizing unused code away, we currently have raminit in ramstage.

Optimize this manually by configuring AGESA_ENTRY booleans for
romstage and ramstage separately. This will remove references in
FuncParamsInfo and DispatchTable -arrays.

All boards now include multi-core dispatcher, it has minimal footprint:
  AGESA_ENTRY_LATE_RUN_AP_TASK

ACPI S3 support depends on HAVE_ACPI_RESUME being enabled:
  AGESA_ENTRY_INIT_RESUME
  AGESA_ENTRY_INIT_LATE_RESTORE
  AGESA_ENTRY_INIT_S3SAVE

Disabled for all boards as it was not used:
  AGESA_ENTRY_INIT_GENERAL_SERVICES

Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14417
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 266 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc
index 985354687e..efc42eec13 100644
--- a/src/vendorcode/amd/agesa/common/Makefile.inc
+++ b/src/vendorcode/amd/agesa/common/Makefile.inc
@@ -27,6 +27,9 @@
 #
 #*****************************************************************************
 
+romstage-y += agesa-entry.c
+ramstage-y += agesa-entry.c
+
 libagesa-y += amdlib.c
 
 # Do not optimise performance-critical low-level IO for size with -Os,
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
new file mode 100644
index 0000000000..e882f2e457
--- /dev/null
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -0,0 +1,86 @@
+#ifndef AGESA_ENTRY_CFG_H
+#define AGESA_ENTRY_CFG_H
+
+
+#if defined(__PRE_RAM__)
+
+#define AGESA_ENTRY_INIT_RESET		TRUE
+#define AGESA_ENTRY_INIT_EARLY		TRUE
+#define AGESA_ENTRY_INIT_POST		TRUE
+
+/* Not implemented in coreboot romstage. */
+#define AGESA_ENTRY_INIT_RECOVERY	FALSE
+
+#define AGESA_ENTRY_INIT_RESUME		IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#define AGESA_ENTRY_INIT_LATE_RESTORE	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+
+/* Move to ramstage? */
+#define AGESA_ENTRY_INIT_ENV		TRUE
+
+#else
+
+#define AGESA_ENTRY_INIT_MID		TRUE
+#define AGESA_ENTRY_INIT_LATE		TRUE
+#define AGESA_ENTRY_INIT_S3SAVE 	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+
+#endif
+
+/* Not required. */
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
+
+/* Required for any multi-core. */
+#define AGESA_ENTRY_LATE_RUN_AP_TASK    TRUE
+
+
+/* Defaults below. */
+
+/*  Process user desired AGESA entry points  */
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               TRUE
+#endif
+
+#endif /* AGESA_ENTRY_CFG_H */
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c
new file mode 100644
index 0000000000..e722fc1de2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/common/agesa-entry.c
@@ -0,0 +1,177 @@
+#include <Porting.h>
+#include <AMD.h>
+#include <AGESA.h>
+
+#include "CommonReturns.h"
+
+#include <heapManager.h>
+#include <CreateStruct.h>
+
+#include <Options.h>
+
+#include <agesa-entry-cfg.h>
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+    { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};