Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.

This code currently generates many warnings that are functionally benign.  These are being addressed, but the wheels of bureaucracy turn slowly.  This drop supports AMD cpu families 10h and 14h.  Only Family 14h is used as an example in this set of patches.  Other cpu families are supported by the infrastructure, but their specific support is not included herein.  This patch is functionally independent of the other patches in this set.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 3652 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.c
new file mode 100644
index 0000000000..dcbbf96969
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.c
@@ -0,0 +1,576 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mns3on.c
+ *
+ * ON memory specific function to support S3 resume
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "mnon.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuCommonF14Utilities.h"
+#include "mnS3on.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNS3ON_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstON (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  );
+
+VOID
+STATIC
+MemNS3SetDfltPllLockTimeON (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+BOOLEAN
+STATIC
+MemNS3ChangeNbFrequencyWrapON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 NBPstate
+  );
+
+VOID
+STATIC
+MemNS3GetConPCIMaskON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+PCI_SPECIAL_CASE PciSpecialCaseFuncON[] = {
+  {MemNS3GetCSRNb, MemNS3SetCSRNb},
+  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb},
+  {MemNS3DisNbPsDbgNb, MemNS3DisNbPsDbgNb},
+  {MemNS3EnNbPsDbg1Nb, MemNS3EnNbPsDbg1Nb},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPllLockTimeON},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDisAutoCompUnb},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeNb},
+  {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}
+};
+
+PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = {
+  {{0, 2, 0}, FUNC_2, 0x110, 0x00000708},
+  {{0, 0, 0}, FUNC_1, 0x40,  0x0FFF0003},
+  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF0000},
+  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF81},
+  {{0, 2, 0}, FUNC_2, 0x114, 0x00000200},
+  {{0, 0, 0}, FUNC_2, 0x118, 0x0F00CFFF},
+  {{0, 0, 0}, FUNC_2, 0x11C, 0x61CC507C},
+  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FED},
+  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FED},
+  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FED},
+  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FED},
+  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0},
+  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0},
+  {{0, 1, 0}, FUNC_2, 0x80,  0x000000FF},
+  {{0, 0, 0}, FUNC_2, 0x84,  0x00FC2FFF},
+  {{0, 0, 0}, FUNC_2, 0x88,  0xFF00000F},
+  {{0, 0, 0}, FUNC_2, 0x8C,  0x03F7FCFF},
+  {{0, 0, 0}, FUNC_2, 0x90,  0x0EF20003},
+  {{0, 1, 0}, FUNC_2, 0xA4,  0x00000007},
+  {{0, 0, 0}, FUNC_2, 0xA8,  0x0078FF1F},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x06), 0x00000F8F},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x16), 0x0000000F},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x40), 0x3F1F0F0F},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x41), 0x00070707},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x83), 0x00007177},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x200), 0x00001F0F},
+
+  // Phy Initialization
+  {{6, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0},
+  // 3. Phy voltage related
+  {{1, 1, 1}, DCT0,   BFDataRxVioLvl, 0x00000018},
+  {{1, 1, 1}, DCT0,   BFClkRxVioLvl, 0x00000018},
+  {{1, 2, 1}, DCT0,   BFCmpVioLvl, 0x0000C000},
+  {{1, 1, 1}, DCT0,   BFCmdRxVioLvl, 0x00000018},
+  {{1, 1, 1}, DCT0,   BFAddrRxVioLvl, 0x00000018},
+  // 4. Frequency Change
+  {{4, 3, 1}, DCT0,   BFPllLockTime, 0},
+  {{0, 0, 0}, FUNC_2, 0x94,  0xFFD1CC1F},
+  //    NB Pstate Related Register for Pstate 0
+  {{0, 0, 0}, FUNC_2, 0x78,  0xFFF63FCF},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F},
+  //   Access NB Pstate 1
+  {{3, 3, 1}, FUNC_6, 0x98, 0},
+  //   NB Pstate Related Register for Pstate 1
+  {{0, 0, 0}, FUNC_2, 0x78,  0xFFF63FCF},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F},
+  //   Disable Access to NB Pstate 1
+  {{2, 3, 1}, FUNC_6, 0x98, 0},
+  {{1, 1, 1}, DCT0,   BFMemClkFreqVal, 0},
+  {{1, 2, 1}, DCT0,   BFPllLockTime, 0},
+  // 5. Phy Fence
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x7FFF3FFF},
+  {{1, 2, 1}, DCT0,   BFDataFence2, 0x00007FFF},
+  {{1, 1, 1}, DCT0,   BFClkFence2, 0x0000001F},
+  {{1, 1, 1}, DCT0,   BFCmdFence2, 0x0000001F},
+  {{1, 1, 1}, DCT0,   BFAddrFence2, 0x0000001F},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x70777777},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F},
+  {{1, 1, 1}, DCT0,   BFDQOdt03, 0x70},
+  {{1, 1, 1}, DCT0,   BFDQOdt47, 0x70},
+  // 6. Phy Compensation Init
+  {{5, 3, 1}, DCT0,   BFDisablePredriverCal, 0},
+  {{1, 2, 1}, DCT0,   BFDataByteTxPreDriverCal2Pad1, 0},
+  {{1, 2, 1}, DCT0,   BFDataByteTxPreDriverCal2Pad2, 0},
+  {{7, 2, 1}, DCT0,   BFDataByteTxPreDriverCal, 0},
+  {{1, 2, 1}, DCT0,   BFCmdAddr0TxPreDriverCal2Pad1, 0},
+  {{1, 2, 1}, DCT0,   BFCmdAddr0TxPreDriverCal2Pad2, 0},
+  {{1, 2, 1}, DCT0,   BFCmdAddr1TxPreDriverCal2Pad1, 0},
+  {{1, 2, 1}, DCT0,   BFCmdAddr1TxPreDriverCal2Pad2, 0},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad1, 0},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad2, 0},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad3, 0},
+  {{1, 2, 1}, DCT0,   BFAddrTxPreDriverCal2Pad4, 0},
+  {{7, 2, 1}, DCT0,   BFCmdAddr0TxPreDriverCalPad0, 0},
+  {{7, 2, 1}, DCT0,   BFCmdAddr1TxPreDriverCalPad0, 0},
+  {{7, 2, 1}, DCT0,   BFAddrTxPreDriverCalPad0, 0},
+  {{7, 2, 1}, DCT0,   BFClock0TxPreDriverCalPad0, 0},
+  {{7, 2, 1}, DCT0,   BFClock1TxPreDriverCalPad0, 0},
+
+  {{1, 2, 1}, DCT0,   BFDisablePredriverCal, 0x00006000}
+};
+
+CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefON = {
+  0,
+  (sizeof (S3PciPreSelfRefDescriptorON) / sizeof (PCI_REG_DESCRIPTOR)),
+  S3PciPreSelfRefDescriptorON,
+  PciSpecialCaseFuncON
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = {
+  // DCT0
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0xFFFFFFFF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0xFFFFFFFF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3E3E3E3E, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3E3E3E3E, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x037F037F, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFPhyClkConfig0, 0x00000010, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFPhyClkConfig1, 0x00000010, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFPhy0x0D0F0F13Bit0to7, 0x00000083, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFAddrCmdTri, 0x0000000B1, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFLowPowerDrvStrengthEn, 0x00000100, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 2, 1}, DCT0,   BFEnRxPadStandby, 0x000001000, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
+
+  {{0, 0, 0}, FUNC_2, 0x1C0, 0x100000, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x84, 0x00060006, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_4, 0x12C, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_4, 0x1A8, 0x3F000000, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x188, 0x00400000, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_6, 0x78, 0x0000FF00, DCT0_MASK, ANY_DIMM_MASK},
+  // Release NB P-state force
+  {{0, 0, 0}, FUNC_6, 0x90, 0x50000000, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, DCT0_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefON = {
+  0,
+  (sizeof (S3CPciPostSelfDescriptorON) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPostSelfDescriptorON,
+  PciSpecialCaseFuncON
+};
+
+MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = {
+  {{0, 0, 0}, 0xC0010010, 0x00000000007F0000},
+  {{0, 0, 0}, 0xC001001A, 0x0000000FFF800000},
+  {{0, 0, 0}, 0xC001001D, 0x0000000FFF800000},
+  {{0, 0, 0}, 0xC001001F, 0x8480FC6A434243E0}
+};
+
+CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefON = {
+  0,
+  (sizeof (S3MSRPreSelfRefDescriptorON) / sizeof (MSR_REG_DESCRIPTOR)),
+  S3MSRPreSelfRefDescriptorON,
+  NULL
+};
+
+VOID *MemS3RegListON[] = {
+  (VOID *)&S3PciPreSelfRefON,
+  NULL,
+  NULL,
+  (VOID *)&S3CPciPostSelfRefON,
+  (VOID *)&S3MSRPreSelfRefON,
+  NULL,
+  NULL,
+  NULL
+};
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for S3 resume
+ *
+ *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
+ *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
+ *     @param[in]       NodeID   - Node ID of the target node.
+ *
+ *      @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN
+MemS3ResumeConstructNBBlockON (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->Ganged = FALSE;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_ON;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  for (i = 0; i < NumberOfHooks; i++) {
+    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
+
+  NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
+  NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedON;
+  NBPtr->ChangeNbFrequencyWrap = MemNS3ChangeNbFrequencyWrapON;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskON;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeClientNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrON;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstON;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0;
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the conditional PCI device mask
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *      @return         none
+ */
+VOID
+STATIC
+MemNS3GetConPCIMaskON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  BIT_FIELD_NAME bitfield;
+  UINT32 RegVal;
+  UINT8 DimmMask;
+
+  DimmMask = 0;
+  for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr3Reg; bitfield ++) {
+    RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
+    if (RegVal & 0x1) {
+      DimmMask |= (UINT8) (1 << (((bitfield - BFCSBaseAddr0Reg) >> 1) << 1));
+    }
+  }
+
+  // Set mask before exit self refresh
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 1;
+  // Set mask after exit self refresh
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 1;
+  // Set DDR3 mask if Dimms present are DDR3
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
+
+  // Set dimm mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the register list for each device for LN
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *     @return          UINT16 - size of the device descriptor on the target node.
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  UINT8 i;
+  UINT16 Size;
+  Size = 0;
+  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
+    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[PCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
+      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_ON + i;
+      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
+    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[CPCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
+      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_ON + i;
+      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->MSRDevice[i].Type = (UINT8)  (DEV_TYPE_MSR_PRE_ESR + i);
+    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[MSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
+      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_ON + i;
+      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
+    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[CMSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
+      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_ON + i;
+      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+    }
+  }
+  return Size;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function return the register list according to the register ID.
+ *
+ *     @param[in]   RegisterLstID - value of the Register list ID.
+ *     @param[out]  **RegisterHeader - pointer to the address of the register list.
+ *     @return      none
+ */
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstON (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  )
+{
+  if (RegisterLstID >= (sizeof (MemS3RegListON) / sizeof (VOID *))) {
+    ASSERT(FALSE); // RegisterListID exceeded size of Register list
+    return AGESA_FATAL;
+  }
+  if (MemS3RegListON[RegisterLstID] != NULL) {
+    *RegisterHeader = MemS3RegListON[RegisterLstID];
+    return AGESA_SUCCESS;
+  }
+  ASSERT(FALSE); // Device regiser list error
+  return AGESA_FATAL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function that set PllLockTime to default state.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetDfltPllLockTimeON (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT16 RegValue;
+
+  RegValue = 0x1838;
+  MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function is a wrapper to call a CPU routine to change NB P-state and
+ *   update NB frequency.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]  *NBPstate - NB Pstate
+ *
+ *     @return          TRUE - Succeed
+ *     @return          FALSE - Fail
+ */
+
+BOOLEAN
+STATIC
+MemNS3ChangeNbFrequencyWrapON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 NBPstate
+  )
+{
+  BOOLEAN Status;
+  UINT32  NBFreq;
+  UINT32  Speed;
+
+  Speed = MemNGetBitFieldNb (NBPtr, BFMemClkFreq);
+  Status = F14NbPstateInit (((Speed + 6) * 3335) / 100,
+                            Speed,
+                            NBPstate,
+                            &NBFreq,
+                            &(NBPtr->MemPtr->StdHeader));
+
+  return Status;
+}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.h
new file mode 100644
index 0000000000..6cb15e75ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.h
@@ -0,0 +1,85 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnS3on.h
+ *
+ * S3 resume memory related function for ON.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _MNS3ON_H_
+#define _MNS3ON_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/// ID for register list of ON
+typedef enum {
+  PCI_LST_ESR_ON,  ///< Assign 0x0000 for PCI register list for pre exit self refresh.
+  PCI_LST_ON,      ///< Assign 0x0001 for PCI register list for post exist self refresh.
+  CPCI_LST_ESR_ON, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
+  CPCI_LST_ON,     ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
+  MSR_LST_ESR_ON,  ///< Assign 0x0004 for MSR register list for pre exit self refresh.
+  MSR_LST_ON,      ///< Assign 0x0005 for MSR register list for post exit self refresh.
+  CMSR_LST_ESR_ON, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
+  CMSR_LST_ON      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
+} RegisterListIDON;
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif //_MNS3ON_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mndcton.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mndcton.c
new file mode 100644
index 0000000000..c0855b8f43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mndcton.c
@@ -0,0 +1,490 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mndcton.c
+ *
+ * Northbridge ON DCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 37169 $ @e \$Date: 2010-09-01 05:35:27 +0800 (Wed, 01 Sep 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
+#include "mnon.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCommonF14Utilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNDCTON_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+#define MAX_RD_DQS_DLY  0x1F
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the memory controller with configuration parameters
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
+ */
+
+BOOLEAN
+MemNAutoConfigON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 PowerDownMode;
+
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  //======================================================================
+  // Build Dram Control Register Value (F2x78)
+  //======================================================================
+  //
+
+  //======================================================================
+  // Build Dram Config Lo Register Value
+  //======================================================================
+  //
+  MemNSetBitFieldNb (NBPtr, BFEnDispAutoPrecharge, 1);
+
+  MemNSetBitFieldNb (NBPtr, BFIdleCycInit, 3);
+
+  //======================================================================
+  // Build Dram Config Hi Register Value
+  //======================================================================
+  //
+
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdClientNb (NBPtr, DCTPtr->Timings.Speed));
+
+  PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHIP_SELECT : UserOptions.CfgPowerDownMode);
+  PowerDownMode = (!NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0;
+  IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+  if (PowerDownMode == 1) {
+    MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1);
+
+  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE);
+
+  MemNSetBitFieldNb (NBPtr, BFDctSelBankSwap, 1);
+
+  //======================================================================
+  // Build Dram Config Misc Register Value
+  //======================================================================
+  //
+  // Max out Non-SPD timings
+  MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x18FF);
+  MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
+  MemNSetBitFieldNb (NBPtr, BFTwrrdSD, 0xA);
+  MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 0x8);
+  MemNSetBitFieldNb (NBPtr, BFTwrwrSD, 0x9);
+
+  MemNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_ON_ON);
+  MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_ON_ON);
+  MemNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, 0);
+
+  //======================================================================
+  // DRAM MRS Register, set ODT
+  //======================================================================
+  MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 1);
+
+  // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
+  MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends an MRS command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendMrsCmdON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetASRSRTNb (NBPtr);
+  MemNSwapBitsNb (NBPtr);
+
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
+
+  // 1.Set SendMrsCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
+
+  // 2.Wait for SendMrsCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function combines all the memory into a contiguous map.
+ *      Requires that Mask values for each bank be programmed first and that
+ *      the chip-select population indicator is correctly set.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNStitchMemoryON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 NxtCSBase;
+  UINT32 CurCSBase;
+  UINT32 CsSize;
+  UINT32 BiggestBank;
+  UINT8 p;
+  UINT8 q;
+  UINT8 BiggestDimm;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  DCTPtr->Timings.CsEnabled = 0;
+  NxtCSBase = 0;
+  for (p = 0; p < MAX_CS_PER_CHANNEL_ON; p++) {
+    BiggestBank = 0;
+    BiggestDimm = 0;
+    for (q = 0; q < MAX_CS_PER_CHANNEL_ON; q++) {
+      if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) {
+        if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) {
+          // (CSEnable|Spare==1)bank is not enabled yet
+          CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1));
+          if (CsSize != 0) {
+            CsSize += ((UINT32)1 << 19);
+            CsSize &= 0xFFF80000;
+          }
+          if (CsSize > BiggestBank) {
+            BiggestBank = CsSize;
+            BiggestDimm = q;
+          }
+        }
+      }
+    }
+
+    if (BiggestBank != 0) {
+      CurCSBase = NxtCSBase;
+      CurCSBase |= ((UINT32)1 << BFCSEnable);
+      NxtCSBase += BiggestBank;
+      if ((BiggestDimm & 1) != 0) {
+        if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) {
+          CurCSBase |= ((UINT32)1 << BFOnDimmMirror);
+        }
+      }
+      MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase);
+      DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm);
+    }
+    if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) {
+      MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail);
+    }
+  }
+
+  if (NxtCSBase != 0) {
+    DCTPtr->Timings.DctMemSize = NxtCSBase >> 8;    // Scale base address from [39:8] to [47:16]
+    NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
+    NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function  sets the maximum round-trip latency in the system from the processor to the DRAM
+ *   devices and back for Ontario.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     MaxRcvEnDly - Maximum receiver enable delay value
+ *
+ */
+
+VOID
+MemNSetMaxLatencyON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  )
+{
+  UINT32 N;
+  UINT32 T;
+  UINT32 P;
+  UINT32 Px2;
+  UINT32 MemClkPeriod;
+
+  AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
+
+  N = 0x50;    // init value for MaxRdLat used in training
+
+  if (MaxRcvEnDly != 0xFFFF) {
+    T = MemNTotalSyncComponentsClientNb (NBPtr);
+
+    // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime))
+    P = ((MaxRcvEnDly + MAX_RD_DQS_DLY) + 31) / 32;
+
+    // P = P + 6.5
+    // T = T + 2586 ps
+    Px2 = (P * 2) + 13;
+    T += 2586;
+
+    // N = (P/(MemClkFreq * 2) + T) * NclkFreq
+    MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+    N = ((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000;
+    N += 2;
+  }
+
+  NBPtr->DCTPtr->Timings.MaxRdLat = (UINT16) N;
+  ASSERT (N <= 0x3FF);
+  IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", N);
+  MemNSetBitFieldNb (NBPtr, BFMaxLatency, N);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function retrieves the Max latency parameters
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @param[in]  *MinDlyPtr - Pointer to variable to store the Minimum Delay value
+ *     @param[in]  *MaxDlyPtr - Pointer to variable to store the Maximum Delay value
+ *     @param[in]  *DlyBiasPtr - Pointer to variable to store Delay Bias value
+ *     @param[in]  MaxDlyForMaxRdLat - Maximum receiver enable delay value
+ *
+ */
+
+VOID
+MemNGetMaxLatParamsClientON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxDlyForMaxRdLat,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  )
+{
+  UINT32 P;
+  UINT32 Px2;
+  UINT32 T;
+  UINT32 MemClkPeriod;
+
+  T = MemNTotalSyncComponentsClientNb (NBPtr);
+
+  // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime))
+  P = (MaxDlyForMaxRdLat + 31) / 32;
+
+  // P = P + 6.5
+  // T = T + 2586 ps
+  Px2 = (P * 2) + 13;
+  T += 2586;
+
+  // N = (P/(MemClkFreq * 2) + T) * NclkFreq
+  MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+
+  *MinDlyPtr = (UINT16) (((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000);
+
+  if (NBPtr->NbFreqChgState == 1) {
+    *MinDlyPtr += 2;
+  } else {
+    *MinDlyPtr += 1;
+  }
+
+  *MaxDlyPtr = 100 + *MinDlyPtr;  // 100 fixed iterations
+
+  // IF ((NCLK!=MEMCLK) && (NCLK!=MEMCLK/2))
+  // THEN TrainingOffset = 3
+  // ELSE TrainingOffset = 2
+  if ((NBPtr->NBClkFreq == NBPtr->DCTPtr->Timings.Speed) ||
+      (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2)) ||
+      (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2 + 1))) {
+    *DlyBiasPtr = 2;
+  } else {
+    *DlyBiasPtr = 3;
+  }
+
+  // Register settings required before MaxRdLat training
+  MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function is a wrapper to call a CPU routine to change NB P-state and
+ *   update NB frequency.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]  *NBPstate - NB Pstate
+ *
+ *     @return          TRUE - Succeed
+ *     @return          FALSE - Fail
+ */
+BOOLEAN
+MemNChangeNbFrequencyWrapON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 NBPstate
+  )
+{
+  BOOLEAN Status;
+  UINT32  NBFreq;
+  UINT32  Memclk;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  if (NBPtr->NbFreqChgState == 0) {
+    // While in state 0, report the new memclk to the
+    // CPU module to adjust the NB P-state settings.
+    Memclk = NBPtr->DCTPtr->Timings.Speed;
+  } else {
+    // We have already adjusted for target memclk.
+    // Indicate NB P-state change only.
+    Memclk = 0;
+  }
+
+  Status = F14NbPstateInit (Memclk,
+                            MemNGetMemClkFreqIdClientNb (NBPtr, NBPtr->DCTPtr->Timings.Speed),
+                            NBPstate,
+                            &NBFreq,
+                            &(NBPtr->MemPtr->StdHeader));
+  if (Status) {
+    // When NB frequency change succeeds, TSC rate may have changed.
+    // We need to update TSC rate
+    GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+    FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
+  }
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function sets Dqs Odt for ON
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *OptParam - Optional parameter
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNSetDqsODTON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && (NBPtr->ChannelPtr->Dimms == 1)) {
+    MemNSetBitFieldNb (NBPtr, BFDQOdt03, 0x20);
+    MemNSetBitFieldNb (NBPtr, BFDQOdt47, 0x20);
+  }
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnflowon.c
new file mode 100644
index 0000000000..b7efd35cbb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnflowon.c
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnflowon.c
+ *
+ * Llano initializer for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_NB_ON_MNFLOWON_FILECODE
+/* features */
+#include "mftds.h"
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the platform specific block
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
+ *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
+ */
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 f;
+
+  if (NBPtr->MCTPtr->DimmValid == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(NBPtr->MemPtr->StdHeader));
+    SetMemError (AGESA_FATAL, NBPtr->MCTPtr);
+    ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found
+    return FALSE; // There is no dimm present on the system.
+  }
+  for (f = 0; memPlatSpecFFInstalledON[f] != NULL; f++) {
+    if (memPlatSpecFFInstalledON[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_SUCCESS) {
+      break;
+    }
+  }
+  if (memPlatSpecFFInstalledON[f] == NULL) {
+    return FALSE; // No FF types are supported
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function selects appropriate Tech functions for the NB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNTechBlockSwitchON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // Specify Dimm-Byte training for Nb
+  MemTDimmByteTrainInit (TechPtr);
+
+  // Remove the following functions because they are not needed for ON
+  TechPtr->SetDramMode = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
+  TechPtr->SpdCalcWidth = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
+  TechPtr->SetDqsEccTmgs = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
+  TechPtr->AdjustTwrwr = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet;
+  TechPtr->AdjustTwrrd = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet;
+  TechPtr->GetLD = (INT8 (*) (MEM_TECH_BLOCK *)) memDefRet;
+  TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyRdDqsDlyByte;
+  TechPtr->ResetDCTWrPtr = (VOID (*) (MEM_TECH_BLOCK *, UINT8)) memDefRet;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnidendimmon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnidendimmon.c
new file mode 100644
index 0000000000..9e4060af3f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnidendimmon.c
@@ -0,0 +1,136 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnidendimmon.c
+ *
+ * ON northbridge constructor for dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
+#include "mnon.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_ON;
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Ganged = FALSE;
+  MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable);
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnmcton.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnmcton.c
new file mode 100644
index 0000000000..6a0ae76c47
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnmcton.c
@@ -0,0 +1,252 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnmcton.c
+ *
+ * Northbridge ON MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 41275 $ @e \$Date: 2010-11-03 02:14:41 +0800 (Wed, 03 Nov 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
+#include "mnon.h"
+#include "mu.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNMCTON_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function create the HT memory map
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNHtMemMapInitON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 WeReMask;
+  UINT32 BottomIo;
+  UINT32 HoleOffset;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  //
+  // Physical addresses in this function are right adjusted by 16 bits ([47:16])
+  // They are BottomIO, HoleOffset, NodeSysBase, NodeSysLimit.
+  //
+
+  // Enforce bottom of IO be be 128MB aligned
+  BottomIo = (RefPtr->BottomIo & 0xF8) << 8;
+
+  NodeSysBase = 0;
+  NodeSysLimit = MCTPtr->NodeMemSize - 1;
+
+  if (NodeSysLimit >= BottomIo) {
+    // HW Dram Remap
+    MCTPtr->Status[SbHWHole] = TRUE;
+    RefPtr->GStatus[GsbHWHole] = TRUE;
+    MCTPtr->NodeHoleBase = BottomIo;
+    RefPtr->HoleBase = BottomIo;
+
+    HoleOffset = _4GB_RJ16 - BottomIo;
+    NodeSysLimit += HoleOffset;
+
+    MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8);
+    MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7);
+    MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1);
+
+  } else {
+    // No Remapping.  Normal Contiguous mapping
+  }
+  MCTPtr->NodeSysBase = NodeSysBase;
+  MCTPtr->NodeSysLimit = NodeSysLimit;
+  RefPtr->SysLimit = MCTPtr->NodeSysLimit;
+
+  WeReMask = 3;
+  // Set the Dram base and set the WE and RE flags in the base.
+  MemNSetBitFieldNb (NBPtr, BFDramBaseReg0, (NodeSysBase << 8) | WeReMask);
+  // Set the Dram limit
+  MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000));
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Report the Uma size that is going to be allocated on Fusion.
+ *     Total system memory   UMASize
+ *     >=2G                   384M
+ *     >=1G                   256M
+ *     <1G                     64M
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          Uma size [31:0] = Addr [47:16]
+ */
+UINT32
+MemNGetUmaSizeON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 SysMemSize;
+  UINT32 SizeOfUma;
+
+  SysMemSize = NBPtr->RefPtr->SysLimit + 1;
+  SysMemSize = (SysMemSize + 0x100) & 0xFFFFF000;   // Ignore 16MB allocated for C6 when finding UMA size
+  if (SysMemSize >= 0x8000) {
+    SizeOfUma = 384 << (20 - 16);
+  } else if (SysMemSize >= 0x4000) {
+    SizeOfUma = 256 << (20 - 16);
+  } else {
+    SizeOfUma = 64 << (20 - 16);
+  }
+
+  return SizeOfUma;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function programs memory prefetch and priority control
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNFinalizeMctON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 MctCfgLoReg;
+  UINT32 MctCfgHiReg;
+
+  // To support ODTS, with assumption that Tref is set to 7.8us always in AGESA
+  MemNSetBitFieldNb (NBPtr, BFDoubleTrefRateEn, 1);
+
+  MctCfgLoReg = MemNGetBitFieldNb (NBPtr, BFMctCfgLoReg);
+  MemNSetBitFieldNb (NBPtr, BFMctCfgLoReg, (MctCfgLoReg & 0xFFFFF000) | 0x04A4);
+
+  MctCfgHiReg = MemNGetBitFieldNb (NBPtr, BFMctCfgHiReg);
+  MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (MctCfgHiReg & 0x9E33AFFF) | 0x00404000);
+
+  // PchgPdTxCClkGateDis is 0 by default
+  // SelCsrPllPdMode and CsrPhySrPllPdMode is 0 by default
+  // SkewMemClk is 0 by default
+
+  //For self-refresh
+  MemNSetBitFieldNb (NBPtr, BFDramSrEn, 1);
+  MemNSetBitFieldNb (NBPtr, BFDramSrHys, 5);
+  if (NBPtr->IsSupported[DramSrHys]) {
+    MemNSetBitFieldNb (NBPtr, BFDramSrHysEn, 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFMemTriStateEn, 1);
+  MemNSetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi, MemNGetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi) | 0x00060006);
+
+  MemNPhyPowerSavingClientNb (NBPtr);
+
+  // Release NB P-state force
+  MemNSetBitFieldNb (NBPtr, BFNbPsCtrlDis, 0);
+  MemNSetBitFieldNb (NBPtr, BFNbPsForceReq, 0);
+
+  IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.c
new file mode 100644
index 0000000000..768d0d7106
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.c
@@ -0,0 +1,456 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnon.c
+ *
+ * Common Northbridge functions for ON
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 40406 $ @e \$Date: 2010-10-22 00:02:12 +0800 (Fri, 22 Oct 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnon.h"
+#include "mu.h"
+#include "merrhdl.h"
+#include "S3.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNON_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamON = {0x1838, 2, 3, 10, 2, 9, 665, 1000};
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
+extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
+ *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
+ *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
+ *
+ *     @retval     Boolean indicating that this is the correct memory
+ *                 controller type for the node number that was passed in.
+ */
+
+BOOLEAN
+MemConstructNBBlockON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem->SocketId, &(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem->LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->SharedPtr = SharedPtr;
+
+  MCTPtr = MemPtr->DiesPerSystem;
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->MCTPtr->NodeId = 0;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader));
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK));
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+    return FALSE;
+  }
+
+  MCTPtr->Dct = 0;
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_ON;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += sizeof (DCT_STRUCT);
+  MCTPtr->DctData->ChannelCount = 1;
+  MCTPtr->DctData->ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += sizeof (CH_DEF_STRUCT);
+  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+
+  //
+  // Initialize Socket List
+  //
+  *(MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr) = MCTPtr->DctData->ChData;
+  *(MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr) = &(MCTPtr->DctData->Timings);
+  MCTPtr->DctData->ChData->ChannelID = 0;
+
+  //
+  // Initialize NB block member variables
+  //
+
+  NBPtr->DCTPtr = NBPtr->MCTPtr->DctData;
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+  NBPtr->ChannelPtr = NBPtr->DCTPtr->ChData;
+
+  MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable);
+  NBPtr->Node = 0;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_ON;
+  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_ON;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON;
+  NBPtr->Ganged = FALSE;
+  NBPtr->PosTrnPattern = POS_PATTERN_256B;
+  NBPtr->MemCleared = FALSE;
+  NBPtr->StartupSpeed = DDR800_FREQUENCY;
+  NBPtr->RcvrEnDlyLimit = 0xFF;
+  NBPtr->DefDctSelIntLvAddr = 3;
+  NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamON;
+  NBPtr->NbFreqChgState = 0;
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  for (i = 0; i < NumberOfHooks; i++) {
+    NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK*, VOID*)) memDefTrue;
+  }
+
+  FeatPtr->InitHwRxEn (NBPtr);
+
+
+  NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
+  NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->SetMaxLatency = MemNSetMaxLatencyON;
+  NBPtr->getMaxLatParams = MemNGetMaxLatParamsClientON;
+  NBPtr->InitializeMCT = (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue;
+  NBPtr->FinalizeMCT = MemNFinalizeMctON;
+  NBPtr->SendMrsCmd = MemNSendMrsCmdON;
+  NBPtr->sendZQCmd = MemNSendZQCmdNb;
+  NBPtr->WritePattern = MemNWritePatternON;
+  NBPtr->ReadPattern = MemNReadPatternON;
+  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
+
+  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
+  NBPtr->InitMCT = MemNInitMCTNb;
+  NBPtr->StitchMemory = MemNStitchMemoryON;
+  NBPtr->AutoConfig = MemNAutoConfigON;
+  NBPtr->PlatformSpec = MemNPlatformSpecUnb;
+  NBPtr->DisableDCT = MemNDisableDCTNb;
+  NBPtr->StartupDCT = MemNStartupDCTUnb;
+  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
+  NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->ChangeFrequency = MemNChangeFrequencyUnb;
+  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
+  NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyNb;
+  NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersClientNb;
+  NBPtr->ProgramCycTimings = MemNProgramCycTimingsClientNb;
+  NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
+  NBPtr->HtMemMapInit = MemNHtMemMapInitON;
+  NBPtr->SyncAddrMapToAllNodes = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
+  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
+  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingON;
+  NBPtr->AfterDqsTraining = MemNAfterDQSTrainingON;
+  NBPtr->OtherTiming = MemNOtherTimingON;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+  NBPtr->TechBlockSwitch = MemNTechBlockSwitchON;
+  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->TrainingFlow = memNTrainFlowControl[DDR3_TRAIN_FLOW];
+  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
+  NBPtr->PollBitField = MemNPollBitFieldNb;
+  NBPtr->BrdcstCheck = MemNBrdcstCheckON;
+  NBPtr->BrdcstSet = MemNSetBitFieldNb;
+  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
+  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->RankEnabled = MemNRankEnabledNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON;
+  NBPtr->MemNBeforeDramInitNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->MemNInitPhyComp = MemNInitPhyCompClientNb;
+  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyClientNb;
+  NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitON;
+  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
+  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsClientNb;
+  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
+  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
+  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
+  NBPtr->CSPerChannel = MemNCSPerChannelON;
+  NBPtr->CSPerDelay = MemNCSPerDelayNb;
+  NBPtr->FlushPattern = MemNFlushPatternNb;
+  NBPtr->GetUmaSize = MemNGetUmaSizeON;
+  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdClientNb;
+  NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
+  NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapON;
+  NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
+  NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
+  NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
+  NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
+  NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
+  NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
+  NBPtr->AllocateC6Storage = MemNAllocateC6StorageClientNb;
+
+  NBPtr->IsSupported[SetDllShutDown] = TRUE;
+  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
+  NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
+  NBPtr->IsSupported[CheckFindPSDct] = TRUE;
+  NBPtr->IsSupported[CheckODTControls] = TRUE;
+  NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE;
+  NBPtr->IsSupported[WLSeedAdjust] = TRUE;
+  NBPtr->IsSupported[ReverseMaxRdLatTrain] = TRUE;
+  NBPtr->IsSupported[DramSrHys] = TRUE;
+  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
+  NBPtr->IsSupported[AdjustTwr] = TRUE;
+  NBPtr->IsSupported[UnifiedNbFence] = TRUE;
+  NBPtr->IsSupported[ChannelPDMode] = TRUE;   // Erratum 435
+
+  NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedON;
+  NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb;
+  NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb;
+  NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] = MemNForceRdDqsPhaseBON;
+  NBPtr->FamilySpecificHook[SetDqsODT] = MemNSetDqsODTON;
+  NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrON;
+
+  FeatPtr->InitCPG (NBPtr);
+  FeatPtr->InitEarlySampleSupport (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+  //
+  // Calculate SPD Offsets per channel and assign pointers
+  // to the data.
+  //
+  NBPtr->MCTPtr->DctData->ChData->SpdPtr = MemPtr->SpdDataStructure;
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes the default values in the MEM_DATA_STRUCT
+ *
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *
+ *     @retval      None
+ */
+VOID
+MemNInitDefaultsON (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &(MemPtr->StdHeader));
+  ASSERT (MemPtr != NULL);
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xE0;
+  RefPtr->UmaMode = UserOptions.CfgUmaMode;
+  RefPtr->UmaSize = UserOptions.CfgUmaSize;
+  RefPtr->MemHoleRemapping = TRUE;
+
+  // Dram Timing
+  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
+  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    MemPtr->SocketList[Socket].ChannelPtr[0] = NULL;
+    MemPtr->SocketList[Socket].TimingsPtr[0] = NULL;
+  }
+
+  // Memory Clear
+  RefPtr->EnableMemClr = TRUE;
+
+  // TableBasedAlterations
+  RefPtr->TableBasedAlterations = NULL;
+
+  // Platform config table
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+
+  // Memory Restore
+  RefPtr->MemRestoreCtl = FALSE;
+  RefPtr->SaveMemContextCtl = FALSE;
+  AmdS3ParamsInitializer (&RefPtr->MemContext);
+
+  // Dram Configuration
+  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
+  RefPtr->EnableNodeIntlv = FALSE;
+  RefPtr->EnableChannelIntlv = FALSE;
+  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
+  RefPtr->EnableParity = FALSE;
+  RefPtr->EnableOnLineSpareCtl = FALSE;
+
+  // Dram Power
+  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
+
+  // ECC
+  RefPtr->EnableEccFeature = FALSE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Pattern[] - Pattern to write
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNWritePatternON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function reads training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Buffer[] - Buffer to fill
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNReadPatternON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUReadCachelines (Buffer, Address, ClCount);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates DQS training for Client NB
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+memNEnableTrainSequenceON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN Retval;
+  Retval = TRUE;
+  if (!MemNIsIdSupportedON (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
+    Retval = FALSE;
+  }
+  return Retval;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.h
new file mode 100644
index 0000000000..e5f8683d36
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.h
@@ -0,0 +1,250 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnon.h
+ *
+ * Ontario Northbridge block
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 37115 $ @e \$Date: 2010-08-31 07:10:42 +0800 (Tue, 31 Aug 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _MNON_H_
+#define _MNON_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CHANNELS_PER_SOCKET_ON    1
+#define MAX_DCTS_PER_NODE_ON          1
+#define MAX_CHANNELS_PER_DCT_ON       1
+#define MAX_DIMMS_PER_CHANNEL_ON      2
+#define MAX_NODES_SUPPORTED_ON        1
+#define MAX_CS_PER_CHANNEL_ON         4
+
+#define DEFAULT_WR_ODT_ON_ON 6
+#define DEFAULT_RD_ODT_ON_ON 6
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemConstructNBBlockON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNInitDefaultsON (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemNSendMrsCmdON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAutoConfigON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNOtherTimingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNCSPerChannelON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNWritePatternON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNReadPatternON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNInitNBRegTableON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   TSEFO NBRegTable[]
+  );
+
+VOID
+MemNBeforeDQSTrainingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNAfterDQSTrainingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNIsIdSupportedON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+UINT32
+MemNCmnGetSetFieldON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+MemNGetUmaSizeON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNBrdcstCheckON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+VOID
+MemNTechBlockSwitchON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNStitchMemoryON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNHtMemMapInitON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSetMaxLatencyON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  );
+
+BOOLEAN
+MemNFinalizeMctON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+memNEnableTrainSequenceON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNChangeNbFrequencyWrapON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 NBPstate
+  );
+
+BOOLEAN
+MemNOverrideRcvEnSeedON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *SeedPtr
+  );
+
+VOID
+MemNGetMaxLatParamsClientON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxDlyForMaxRdLat,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  );
+
+BOOLEAN
+MemNForceRdDqsPhaseBON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *RdDqsDlyPtr
+  );
+
+BOOLEAN
+MemNSetDqsODTON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+MemNResetRxFifoPtrON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+#endif  /* _MNON_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnoton.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnoton.c
new file mode 100644
index 0000000000..3fe33d666c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnoton.c
@@ -0,0 +1,230 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnoton.c
+ *
+ * Northbridge Non-SPD timings for ON
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 39158 $ @e \$Date: 2010-10-07 21:34:36 +0800 (Thu, 07 Oct 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
+#include "mnon.h"
+#include "mu.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNOTON_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNSetOtherTimingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemNPowerDownCtlON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the non-SPD timings
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNOtherTimingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetOtherTimingON (NBPtr);
+  MemNPowerDownCtlON (NBPtr);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the non-SPD timings into the PCI registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNSetOtherTimingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT16 ROD;
+  INT16 WOD;
+  UINT8 LD;
+  UINT8 Tcwl;
+  INT16 CDDTrdrd;
+  INT16 Trdrd;
+  INT16 CDDTwrwr;
+  INT16 Twrwr;
+  INT16 CDDTwrrdSD;
+  INT16 TwrrdSD;
+  INT16 CDDTwrrd;
+  INT16 Twrrd;
+  INT16 CDDTrwtTO;
+  INT16 TrwtTO;
+
+  ROD = (DEFAULT_RD_ODT_ON_ON > 6) ? (DEFAULT_RD_ODT_ON_ON - 6) : 0;
+  WOD = (DEFAULT_RD_ODT_ON_ON > 6) ? (DEFAULT_WR_ODT_ON_ON - 6) : 0;
+
+  Tcwl = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) + 2;
+  LD = NBPtr->DCTPtr->Timings.CasL - Tcwl;
+
+  // TrdrdSD = 3
+  MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 2 - 2 + 1);
+
+  // Trdrd = CEIL(MAX(ROD + 3, CDDTrdrd/2 + (F2x[94]SlowAccessMode ? 3 : 3.5)))
+  CDDTrdrd = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE) + (INT16) ((NBPtr->ChannelPtr->SlowMode ? 6 : 7) + 1)) / (INT16) 2;
+  Trdrd = MAX (ROD + 3, CDDTrdrd);
+  Trdrd = MIN (MAX (Trdrd, 2), 10);
+  MemNSetBitFieldNb (NBPtr, BFTrdrd, (UINT8) (Trdrd - 2));
+
+  // TwrwrSD = WOD + 3
+  MemNSetBitFieldNb (NBPtr, BFTwrwrSD, (WOD + 3 - 1));
+
+  // Twrwr = CEIL(MAX(WOD + 3, CDDTwrwr / 2 + 3.5))
+  CDDTwrwr = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE) + (INT16) (7 + 1)) / (INT16) 2;
+  Twrwr = MAX (WOD + 3, CDDTwrwr);
+  Twrwr = MIN (MAX (Twrwr, 1), 10);
+  MemNSetBitFieldNb (NBPtr, BFTwrwr, (UINT8) (Twrwr - 1));
+
+  // TwrrdSD = CEIL(MAX(1, MAX(WOD, CDDTwrrdSD / 2 + 0.5) - LD + 3))
+  CDDTwrrdSD = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, TRUE, FALSE) + (INT16) (1 + 1)) / (INT16) 2;
+  TwrrdSD = MAX (WOD, CDDTwrrdSD) - LD + 3;
+  TwrrdSD = MIN (MAX (TwrrdSD, 1), 11);
+  MemNSetBitFieldNb (NBPtr, BFTwrrdSD, (UINT8) (TwrrdSD - 1));
+
+  // Twrrd = CEIL(MAX(1, MAX(WOD, CDDTwrrd / 2 + 0.5) - LD + 3))
+  CDDTwrrd = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, FALSE, TRUE) + (INT16) (1 + 1)) / (INT16) 2;
+  Twrrd = MAX (WOD, CDDTwrrd) - LD + 3;
+  Twrrd = MIN (MAX (Twrrd, 1), 11);
+  Twrrd = MAX (Twrrd, TwrrdSD);
+  MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT8) (Twrrd - 1));
+
+  // TrwtTO = CEIL(MAX(ROD, CDDTrwtTO / 2 - 0.5) + LD + 3).
+  CDDTrwtTO = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE) + (INT16) (1 - 1)) / (INT16) 2;
+  TrwtTO = MAX (ROD, CDDTrwtTO) + LD + 3;
+  TrwtTO = MIN (MAX (TrwtTO, 3), 17);
+  MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT8) (TrwtTO - 2));
+
+  // TrwtWB should be set to 0xF for ON.
+  MemNSetBitFieldNb (NBPtr, BFTrwtWB, 4);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function enables power down mode
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNPowerDownCtlON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->RefPtr->EnablePowerDown) {
+    MemNSetTxpNb (NBPtr);
+    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+  }
+
+  if (NBPtr->RefPtr->EnableBankSwizzle) {
+    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnphyon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnphyon.c
new file mode 100644
index 0000000000..e20b8cc3d9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnphyon.c
@@ -0,0 +1,244 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnphyon.c
+ *
+ * Northbridge Phy support for ON
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 37401 $ @e \$Date: 2010-09-03 05:32:06 +0800 (Fri, 03 Sep 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "merrhdl.h"
+#include "OptionMemory.h"       // need def for MEM_FEAT_BLOCK_NB
+#include "mnon.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNPHYON_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CS_PER_CHANNEL_ON 4
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDQSTrainingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemTBeginTraining (NBPtr->TechPtr);
+
+  MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
+  MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
+  MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0);
+  MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0);
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0);
+  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1);
+  MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1F);
+  MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 1);
+  MemNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0);
+  MemNSetBitFieldNb (NBPtr, BFMaxLatency, 0x12);
+  MemNSetBitFieldNb (NBPtr, BFTraceModeEn, 0);
+
+  // Enable cut through mode for NB P0
+  MemNSetBitFieldNb (NBPtr, BFDisCutThroughMode, 0);
+
+  MemTEndTraining (NBPtr->TechPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes after DRAM training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNAfterDQSTrainingON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) {
+    MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1);
+  }
+  MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
+  MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
+  MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1C);
+  MemNSetBitFieldNb (NBPtr, BFDramTrainPdbDis, 1);
+  MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the number of chipselects per channel of Ontario.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return
+ */
+
+UINT8
+MemNCSPerChannelON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return MAX_CS_PER_CHANNEL_ON;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function overrides the seed for hardware based RcvEn training of Ontario.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *SeedPtr - Pointer to the seed value.
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNOverrideRcvEnSeedON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *SeedPtr
+  )
+{
+  *(UINT16*) SeedPtr = 0x5B;
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function force the Rd Dqs Delay to phase B (0x20)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *RdDqsDlyPtr - Pointer to Rd DQS delay.
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNForceRdDqsPhaseBON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *RdDqsDlyPtr
+  )
+{
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && (*(UINT8 *) RdDqsDlyPtr < 0x20)) {
+    *(UINT8 *) RdDqsDlyPtr = 0x20;
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function resets RxFifo pointer during Read DQS training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *OptParam - Optional parameter
+ *
+ *     @return    TRUE
+ */
+
+BOOLEAN
+MemNResetRxFifoPtrON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  if (NBPtr->TechPtr->Direction == DQS_READ_DIR) {
+    MemNSetBitFieldNb (NBPtr, BFRxPtrInitReq, 1);
+    MemNPollBitFieldNb (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  }
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnprotoon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnprotoon.c
new file mode 100644
index 0000000000..d8c9c9df59
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnprotoon.c
@@ -0,0 +1,165 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnprotoon.c
+ *
+ * Northbridge support functions for Errata and early samples
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 37691 $ @e \$Date: 2010-09-10 04:28:23 +0800 (Fri, 10 Sep 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "cpuRegisters.h"
+#include "AdvancedApi.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNPROTOON_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNForceAutoCompON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
+STATIC
+MemNDetectMemPllErrorON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function initializes early sample support for Ontario
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNInitEarlySampleSupportON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_A0) != 0) {
+    NBPtr->IsSupported[DramSrHys] = FALSE;      // UBTS 233978
+    NBPtr->NBRegTable[BFRxMaxDurDllNoLock] = 0;
+    NBPtr->NBRegTable[BFTxMaxDurDllNoLock] = 0;
+    NBPtr->FamilySpecificHook[ForceAutoComp] = MemNForceAutoCompON;
+  }
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & (AMD_F14_ON_A0 | AMD_F14_ON_A1)) != 0) {
+    NBPtr->FamilySpecificHook[DetectMemPllError] = MemNDetectMemPllErrorON;
+  }
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function forces auto compensation to be disabled all the time for
+ *     ON A0
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNForceAutoCompON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFPNOdtCal, 0x2020);
+  MemNSetBitFieldNb (NBPtr, BFPNDrvCal, 0x8080);
+  MemNSetBitFieldNb (NBPtr, BFCalVal, 0x8000);
+
+  return TRUE;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function detects MemPll divide by 3 bug
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNDetectMemPllErrorON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  UINT16 Value;
+
+  Value = 0xFFFF;
+  if ((*(UINT8 *) OptParam) < 5) {
+    LibAmdIoWrite (AccessWidth16, IDS_DEBUG_PORT, &Value, &NBPtr->MemPtr->StdHeader);
+  }
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnregon.c
new file mode 100644
index 0000000000..3f99b2c590
--- /dev/null
+++ b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnregon.c
@@ -0,0 +1,600 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mnregon.c
+ *
+ * Common Northbridge register related functions for ON
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/ON)
+ * @e \$Revision: 39747 $ @e \$Date: 2010-10-15 02:58:08 +0800 (Fri, 15 Oct 2010) $
+ *
+ **/
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnon.h"
+#include "merrhdl.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_ON_MNREGON_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define PHY_DIRECT_ADDRESS_MASK   0x0D000000
+
+STATIC CONST UINT8 InstancesPerTypeON[8] = {8, 2, 1, 0, 2, 0, 1, 1};
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a Ontario.
+ *     @return          FALSE - This node is not a Ontario.
+ */
+BOOLEAN
+MemNIsIdSupportedON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+  if (((LogicalIdPtr->Family & AMD_FAMILY_14_ON) != 0)
+      && ((LogicalIdPtr->Revision & AMD_F14_ALL) != 0)) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
+ *  DCTs that are disabled.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be checked
+ *
+ *     @return          TRUE -  All enabled DCTs have the expected value on the bitfield.
+ *     @return          FALSE - Not all enabled DCTs have the expected value on the bitfield.
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNBrdcstCheckON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) {
+    return FALSE;
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field to be programmed
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNCmnGetSetFieldON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  TSEFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT8 IsLinked;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+  UINT8  IsPhyDirectAccess;
+  UINT8  IsWholeRegAccess;
+  UINT8  NumOfInstances;
+  UINT8  Instance;
+
+  Value = 0;
+  if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = (UINT8) TSEFO_TYPE (Address);
+      IsLinked = (UINT8) TSEFO_LINKED (Address);
+      IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address);
+      IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address);
+
+      ASSERT ((Address & ((UINT32) 1) << 29) == 0);   // Old Phy direct access method is not supported
+
+      Address = TSEFO_OFFSET (Address);
+
+      // By default, a bit field has only one instance
+      NumOfInstances = 1;
+
+      if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
+        Address |= PHY_DIRECT_ADDRESS_MASK;
+        if (IsWholeRegAccess) {
+          // In the case of whole regiter access (bit 0 to 15),
+          // HW broadcast and nibble mask will be used.
+          Address |= Lowbit << 16;
+          Lowbit = 0;
+          Highbit = 15;
+        } else {
+          // In the case only some bits on a register is accessed,
+          // BIOS will do read-mod-write to all chiplets manually.
+          // And nibble mask will be 1111b always.
+          Address |= 0x000F0000;
+          Field >>= Lowbit;
+          if ((Address & 0x0F00) == 0x0F00) {
+            // Broadcast mode
+            // Find out how many instances to write to
+            NumOfInstances = InstancesPerTypeON[(Address >> 13) & 0x7];
+            if (!IsSet) {
+              // For read, only read from instance 0 in broadcast mode
+              NumOfInstances = 1;
+            }
+          }
+        }
+      }
+
+      ASSERT (NumOfInstances > 0);
+
+      for (Instance = 0; Instance < NumOfInstances; Instance++) {
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+          PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+          PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+          Address = PciAddr.AddressValue;
+          LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+          if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
+              (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
+            IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value);
+          }
+        } else if (Type == DCT_PHY_ACCESS) {
+          if (IsPhyDirectAccess && (NumOfInstances > 1)) {
+            Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8);
+          }
+          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+          Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
+        } else if (Type == DCT_EXTRA) {
+          MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+          Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
+          IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
+        } else {
+          IDS_ERROR_TRAP;
+        }
+
+        if (IsSet) {
+          // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+          if ((Highbit - Lowbit) != 31) {
+            Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+          } else {
+            Mask = (UINT32)0xFFFFFFFF;
+          }
+          Value &= ~(Mask << Lowbit);
+          Value |= (Field & Mask) << Lowbit;
+
+          if (Type == NB_ACCESS) {
+            PciAddr.AddressValue = Address;
+            LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+            if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
+                (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
+              IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
+            }
+          } else if (Type == DCT_PHY_ACCESS) {
+            MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+            Address |= DCT_ACCESS_WRITE;
+            MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+            MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+            IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
+          } else if (Type == DCT_EXTRA) {
+            MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
+            Address |= DCT_ACCESS_WRITE;
+            MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
+            MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+            IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
+          } else {
+            IDS_ERROR_TRAP;
+          }
+          if (IsLinked) {
+            MemNCmnGetSetFieldON (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
+          }
+        } else {
+          Value = Value >> Lowbit;  // Shift
+          // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+          if ((Highbit - Lowbit) != 31) {
+            Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+          }
+          if (IsLinked) {
+            Value |= MemNCmnGetSetFieldON (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
+          }
+          // For direct phy access, shift the bit back for compatibility reason.
+          if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
+            Value <<= Lowbit;
+          }
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   NBRegTable[]   - Pointer to the bit field data structure
+ *
+ */
+
+VOID
+MemNInitNBRegTableON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   TSEFO NBRegTable[]
+  )
+{
+  UINT16 i;
+  for (i = 0; i < BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31,  0, BFDctExtraOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  6,  6, BFRxPtrInitReq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 20, 20, BFForceCasToSlot0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 21, 21, BFDisCutThroughMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 22, 21, BFIdleCycInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFEnDispAutoPrecharge);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 26, 26, BFDbeSkidBufDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  4,  0, BFMemClkFreq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  7,  7, BFMemClkFreqVal);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  0,  0, BFDoubleTrefRateEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  2,  1, BFThrottleEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xAC), 0, 0, BFMemTempHot);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0),  0,  0, BFTraceModeEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114),  9,  9, BFDctSelBankSwap);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFC6DramLock);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFDctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 23, 23, BFRdTrainGo);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 22, 22, BFRdDramTrainMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 20, 20, BFDramTrainPdbDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 17,  2, BFTrainLength);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0),  1,  1, BFWrTrainGo);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0),  0,  0, BFWrDramTrainMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C8), 31,  0, BFWrTrainAdrPtrLo);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1CC), 17, 16, BFWrTrainAdrPtrHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D0),  9,  0, BFWrTrainBufAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D4), 31,  0, BFWrTrainBufDat);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 15,  8, BFTrainCmpSts2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8),  7,  0, BFTrainCmpSts);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 19, 19, BFNclkFreqDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  5,  0, BFMainPllOpFreqId);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 26, 20, BFNbPs0NclkDiv);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 22, 22, BFEnCpuSerRdBehindNpIoWr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90),  6,  0, BFNbPs1NclkDiv);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 28, 28, BFNbPsForceReq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 30, 30, BFNbPsCtrlDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 30, 30, BFNbPsCsrAccSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 31, 31, BFNbPsDbgEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x12C), 11,  0, BFC6Base);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x164),  0,  0, BFFixedErrataSkipPorFreqCap);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 29, 29, BFDramSrHysEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 28, 26, BFDramSrHys);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31,  0, BFAcpiPwrStsCtrlHi);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  2,  0, BFCkeDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  6,  4, BFCsOdtDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10,  8, BFAddrCmdDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 30, 28, BFProcOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  4,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  7,  6, BFFenceTrSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31,  0, BFDramPhyStatusReg);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11,  8, BFODTTri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C,  7,  0, BFChipSelTri);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D,  9,  8, BFTxDLLWakeupTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D,  6,  4, BFTxCPUpdPeriod);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D,  3,  0, BFTxMaxDurDllNoLock);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13,  7,  0, BFPhy0x0D0F0F13Bit0to7);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15,  0, BFPllLockTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030,  4,  4, BFPhyClkConfig0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130,  4,  4, BFPhyClkConfig1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000,  8,  8, BFLowPowerDrvStrengthEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15,  0, BFAddrCmdTri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14,  0, BFDataFence2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31,  4,  0, BFClkFence2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31,  4,  0, BFCmdFence2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031,  4,  0, BFAddrFence2);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15,  0, BFDataByteTxPreDriverCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15,  0, BFDataByteTxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15,  0, BFDataByteTxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15,  0, BFCmdAddr0TxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15,  0, BFCmdAddr0TxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15,  0, BFCmdAddr1TxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15,  0, BFCmdAddr1TxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15,  0, BFAddrTxPreDriverCal2Pad1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15,  0, BFAddrTxPreDriverCal2Pad2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15,  0, BFAddrTxPreDriverCal2Pad3);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15,  0, BFAddrTxPreDriverCal2Pad4);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15,  0, BFCmdAddr0TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15,  0, BFCmdAddr1TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15,  0, BFAddrTxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15,  0, BFClock0TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15,  0, BFClock1TxPreDriverCalPad0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1C00, 15,  0, BFPNOdtCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1D00, 15,  0, BFPNDrvCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D081E00, 15,  0, BFCalVal);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F,  4,  3, BFDataRxVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F,  4,  3, BFClkRxVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F,  4,  3, BFCmdRxVioLvl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F,  4,  3, BFAddrRxVioLvl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15,  0, BFPhy0x0D080F0C);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00,  6,  4, BFDQOdt03);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08,  6,  4, BFDQOdt47);
+
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11,  8, BFTwrrdSD);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06,  3,  0, BFTrdrdSD);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16,  3,  0, BFTwrwrSD);
+
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12,  0, BFDbeGskFifoNumerator);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12,  0, BFDbeGskFifoDenominator);
+
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32,  4,  0, BFDataTxFifoSchedDlySlot0);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32,  7,  7, BFDataTxFifoSchedDlyNegSlot0);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 12,  8, BFDataTxFifoSchedDlySlot1);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1);
+
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40,  3,  0, BFTrcd);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 11,  8, BFTrp);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 20, 16, BFTras);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 29, 24, BFTrc);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41,  2,  0, BFTrtp);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 10,  8, BFTrrd);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 18, 16, BFTwtr);
+
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83,  2,  0, BFRdOdtTrnOnDly);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83,  6,  4, BFRdOdtOnDuration);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83,  8,  8, BFWrOdtTrnOnDly);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 14, 12, BFWrOdtOnDuration);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFRdOdtPatReg);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFWrOdtPatReg);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200,  3, 0, BFTxp);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 12, 8, BFTxpdll);
+
+  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
+  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
+  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
+}