diff options
| author | Frank Vibrans <frank.vibrans@amd.com> | 2011-02-14 18:30:54 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-14 18:30:54 +0000 |
| commit | 2b4c831b4d16b55a7abdea20bce82cccd168232c (patch) | |
| tree | 95a35c737d16119f1dfa9c1c9d7700710d8a04f7 /src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY | |
| parent | 74ad66cdc143e04f976ba21e538e02b20362d7e6 (diff) | |
Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
This code currently generates many warnings that are functionally benign. These are being addressed, but the wheels of bureaucracy turn slowly. This drop supports AMD cpu families 10h and 14h. Only Family 14h is used as an example in this set of patches. Other cpu families are supported by the infrastructure, but their specific support is not included herein. This patch is functionally independent of the other patches in this set.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY')
7 files changed, 2243 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c new file mode 100644 index 0000000000..6b43faabd0 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Hydra Equivalence Table related data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] = +{ + 0x1080, 0x1080, + 0x1081, 0x1081, + 0x1091, 0x1081 +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate microcode patch equivalent ID table. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] HyEquivalenceTablePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10HyMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **HyEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c new file mode 100644 index 0000000000..fd8d90b1c1 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c @@ -0,0 +1,1295 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Hydra Ht Phy tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// HT Phy T a b l e s +// ------------------------- +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyHtPhyRegisters[] = +{ +// 0x60:0x68 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0x60, 0x68, // Address + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0x70:0x78 + { + HtPhyRangeRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0x70, 0x78, // Address + 0x00000040, // regData + 0x00000040, // regMask + } + }, +// 0xC0 + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0xC0, // Address + 0x40040000, // regData + 0xe01F0000, // regMask + } + }, +// 0xD0 + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0xD0, // Address + 0x40040000, // regData + 0xe01F0000, // regMask + } + }, +// 0xCF +// Default for HT3, unless overridden below. + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_HT3, // + 0xCF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// Default for HT3, unless overridden below. + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_HT3, // + 0xDF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, + +// +// All the entries for XmtRdPtr 6 +// + +// 0xCF +// For HT frequencies 1200-1600 and NB Freq 1600, 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1200-1600 and NB Freq 1600, 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 1800 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1800 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 3200 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 3200 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000006A, // regData + 0x000000FF, // regMask + } + }, + +// +// Entries for XmtRdPtr 5 +// + +// 0xCF +// For HT frequencies 1800-2600 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1800-2600 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2000 - 2800 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2000 - 2800 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000005A, // regData + 0x000000FF, // regMask + } + }, + +// +// Entries for XmtRdPtr 4 +// + +// 0xCF +// For HT frequencies 2800-3000 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2800-3000 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 3000 - 3200 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 3000 - 3200 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000004A, // regData + 0x000000FF, // regMask + } + }, + +// +// Entries for XmtRdPtr 3 +// + +// 0xCF +// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, + +// +// Rev D0 fixups for Erratum 398. +// + +// 0xCF +// For HT frequencies 1800, 2200 and NB Freq 1400 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000000A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1800, 2200 and NB Freq 1400 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000000A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2600, 3000 and NB Freq 1400 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000000A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2600, 3000 and NB Freq 1400 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000000A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2200, 2600 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2200, 2600 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 3000 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 3000 and NB Freq 1600 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2200, 2600 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2200, 2600 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 3000 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 3000 and NB Freq 1800 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 1800 and NB Freq 1600 for all links + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3), + 0xCF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 1800 and NB Freq 1600 for all links + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7), + 0xDF, // Address + 0x0000003A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000002A, // regData + 0x000000FF, // regMask + } + }, +// 0xCF +// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL0_LINK1), + 0xCF, // Address + 0x0000001A, // regData + 0x000000FF, // regMask + } + }, +// 0xDF +// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1 + { + HtPhyFreqRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)), + (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE), + (HTPHY_LINKTYPE_SL1_LINK5), + 0xDF, // Address + 0x0000001A, // regData + 0x000000FF, // regMask + } + }, + +// +// Deemphasis Settings for D1 processors. +// + +// For D1, also set [7]TxLs23ClkGateEn. +//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6] +// No deemphasis 00h 00h 00h 0 0 0 0 +// -3dB postcursor 12h 00h 00h 1 0 0 0 +// -6dB postcursor 1Fh 00h 00h 1 0 0 0 +// -8dB postcursor 1Fh 06h 00h 1 1 0 1 +// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1 +// -11dB postcursor with +// -8dB precursor 1Fh 06h 07h 1 1 1 1 + + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL_NONE, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x00000080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__3, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x80120080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__6, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0x801F0080, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F06C0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xC01F0DC0, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL0_HT3, // + 0xC5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, + { + DeemphasisRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + DEEMPHASIS_LEVEL__11_8, + HTPHY_LINKTYPE_SL1_HT3, // + 0xD5, // Address + 0xE01F06C7, // regData + 0xE01F1FDF, // regMask + } + }, + +// 0x520A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL0_ALL, // + 0x520A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, +// 0x530A + { + HtPhyRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_HY_ALL // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + HTPHY_LINKTYPE_SL1_ALL, // + 0x530A, // Address + 0x00004000, // regData + 0x00006000, // regMask + } + }, +}; + +CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable = { + PrimaryCores, + (sizeof (F10HyHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10HyHtPhyRegisters, +}; diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c new file mode 100644 index 0000000000..ecb0b0d987 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c @@ -0,0 +1,137 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Implements the workaround for erratum 419. + * + * Returns the table of initialization steps to perform at + * AmdInitEarly. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10/RevD/HY + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "F10PackageType.h" +#include "cpuEarlyInit.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; +extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable; + +CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] = +{ + {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET}, + {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {NULL, 0} +}; + +/*------------------------------------------------------------------------------------*/ +/** + * Initializer routine that may be invoked at AmdCpuEarly to return the steps + * appropriate for the executing Rev D core. + * + * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[out] Table Table of appropriate init steps for the executing core. + * @param[in] EarlyParams Service Interface structure to initialize. + * @param[in] StdHeader Opaque handle to standard config header. + * + */ +VOID +GetF10HyEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProcessorPackageType; + CPU_LOGICAL_ID LogicalId; + + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + ProcessorPackageType = LibAmdGetPackageType (StdHeader); + + // Check if this CPU is affected by erratum 419. + if (((LogicalId.Revision & AMD_F10_HY_SCM_D0) != 0) && ((ProcessorPackageType & (PACKAGE_TYPE_G34 | PACKAGE_TYPE_FR2_FR5_FR6)) == 0)) { + // Return initialization steps such that the microcode patch is applied before + // brand string determination is performed. + *Table = F10HyC32D0EarlyInitOnCoreTable; + } else { + // No workaround is necessary. Return the standard table. + GetF10EarlyInitOnCoreTable (FamilyServices, Table, EarlyParams, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c new file mode 100644 index 0000000000..f0362f0edc --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Hydra Logical ID Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10HyLogicalIdAndRevArray[] = +{ + { + 0x1080, + AMD_F10_HY_SCM_D0 + }, + { + 0x1090, + AMD_F10_HY_MCM_D0 + }, + { + 0x1081, + AMD_F10_HY_SCM_D1 + }, + { + 0x1091, + AMD_F10_HY_MCM_D1 + } +}; + +VOID +GetF10HyLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **HyIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF10HyLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); + *HyIdPtr = CpuF10HyLogicalIdAndRevArray; + *LogicalFamily = AMD_FAMILY_10_HY; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c new file mode 100644 index 0000000000..5d9555ca18 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Hydra PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +extern CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns a table containing the appropriate microcode patches. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] HyUcodePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF10HyMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **HyUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = CpuF10HyNumberOfMicrocodePatches; + *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0]; +} + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c new file mode 100644 index 0000000000..82a52e3495 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c @@ -0,0 +1,138 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 HY MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + +// MSR_LS_CFG (0xC0011020) +// bit[1] = 0 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_B0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_LS_CFG, // MSR Address + 0x0000000000000000, // OR Mask + (1 << 1) // NAND Mask + } + }, + +// MSR_BU_CFG (0xC0011023) +// bit[21] = 1 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_B0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_BU_CFG, // MSR Address + (1 << 21), // OR Mask + (1 << 21), // NAND Mask + } + }, + +// MSR_BU_CFG2 (0xC001102A) +// bit[50] = 1 +// For GH rev C1 and later [RdMmExtCfgQwEn]=1 + { + MsrRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_C0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MSR_BU_CFG2, // MSR Address + 0x0004000000000000, // OR Mask + 0x0004000000000000, // NAND Mask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = { + AllCores, + (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters, +}; + + diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c new file mode 100644 index 0000000000..18026de0b4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c @@ -0,0 +1,350 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_10 Hydra PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x10 + * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyPciRegisters[] = +{ +// F0x68 - + // BufRelPri for rev D + // bits[14:13] BufRelPri = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Dx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address + 0x00002000, // regData + 0x00006000, // regMask + } + }, +// F0x150 - Link Global Retry Control Register +// bit[18:16] TotalRetryAttempts = 7 +// bit[13] HtRetryCrcDatInsDynEn = 1 +// bit[12]HtRetryCrcCmdPackDynEn = 1 +// bit[11:9] HtRetryCrcDatIns = 0 +// bit[8] HtRetryCrcCmdPack = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address + 0x00073100, // regData + 0x00073F00, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[15:13] ForceFullT0 = 6 +// bit[5:0] T0Time = 0x26 + { + PciRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x0000C026, // regData + 0x0000E03F, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[9] RXCalEn = 1 + { + PciRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_Dx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x00000200, // regData + 0x00000200, // regMask + } + }, +// F0x16C - Link Global Extended Control Register +// bit[7:6] InLnSt = 01b (PHY_OFF) + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Dx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address + 0x00000040, // regData + 0x000000C0, // regMask + } + }, +// F0x[18C:170] - Link Extended Control Register - All connected links. +// bit[8] LS2En = 1 + { + HtLinkPciRegister, + { + AMD_FAMILY_10_HY, // CpuFamily + AMD_F10_D1 // CpuRevision + }, + AMD_PF_ALL, // platform Features + { + HT_HOST_FEATURES_ALL, + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address + 0x00000100, // regData + 0x00000100, // regMask + } + }, +// F2x1B0 - Extended Memory Controller Configuration Low +// bits[10:8], CohPrefPrbLmt = 0 + { + ProfileFixup, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Dx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + PERFORMANCE_PROBEFILTER, // Features + MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address + 0x00000000, // regData + 0x00000700, // regMask + } + }, +// Function 3 - Misc. Control +// F3x158 - Link to XCS Token Count +// bits[3:0] LnkToXcsDRToken = 3 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_A2 // CpuRevision + }, + AMD_PF_UMA, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address + 0x00000003, // regData + 0x0000000F, // regMask + } + }, + +// F3x80 - ACPI Power State Control +// ACPI State C2 +// bits[0] CpuPrbEn = 1 +// bits[1] NbLowPwrEn = 0 +// bits[2] NbGateEn = 0 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 1 +// ACPI State C3, C1E or Link init +// bits[0] CpuPrbEn = 0 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 1 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 5 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_Ax // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x0000A681, // regData + 0x0000FFFF, // regMask + } + }, + +// F3x80 - ACPI Power State Control +// ACPI State C3, C1E or Link init +// bits[0] CpuPrbEn = 0 +// bits[1] NbLowPwrEn = 1 +// bits[2] NbGateEn = 1 +// bits[3] NbCofChg = 0 +// bits[4] AltVidEn = 0 +// bits[7:5] ClkDivisor = 7 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address + 0x0000E600, // regData + 0x0000FF00, // regMask + } + }, + +// F3xA0 - Power Control Miscellaneous +// bit[14] BpPinsTriEn = 1 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_GT_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x00004000, // regData + 0x00004000, // regMask + } + }, + +// F3x188 - NB Extended Configuration Low Register +// bit[27] = DisCpuWrSzDw64ReOrd + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address + 0x08000000, // regData + 0x08000000, // regMask + } + }, + +// F3x1B8 - L3 Control +// bit[18] L3RdBufBypDis = 1, Erratum 374 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_D0 // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address + 0x00040000, // regData + 0x00040000, // regMask + } + }, + +// F3x1B8 - L3 Control +// bit[23] L3BankSwapDis = 1, Erratum 385 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Dx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address + 0x00800000, // regData + 0x00800000, // regMask + } + }, + +// F3x1D4 - Probe Filter Control Register +// bits[21:20] PFPreferedSORepl = 2 + { + PciRegister, + { + AMD_FAMILY_10, // CpuFamily + AMD_F10_Dx // CpuRevision + }, + AMD_PF_ALL, // platformFeatures + { + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1D4), // Address + 0x00200000, // regData + 0x00300000, // regMask + } + } +}; + +CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = { + PrimaryCores, + (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F10HyPciRegisters, +}; + |