soc/intel/cannonlake: Add PrmrrSize and C6DRAM config

This patch ensures coreboot can set PRMRR size and C6DRAM
enable FSP-M UPDs.

Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions