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authorShaunak Saha <shaunak.saha@intel.com>2016-09-09 11:43:03 -0700
committerAaron Durbin <adurbin@chromium.org>2016-09-15 03:16:46 +0200
commitc8ae5995bb24006949dee02148c806e6de74aa2c (patch)
tree2ece43f0eb431ad42bbf78b0f8e749631c0b3cbe /src/vboot/vboot_handoff.c
parent629ca4385996708e750c06f31d5fb4f2139cc978 (diff)
soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before going to S3. But this won't work for S0iX as it happens from Linux kernel and SMI handler is not involved in that flow. We need to set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux kernel before going to sleep checks what values are passed through ASL as wake events (through _PRW), keeps those enabled only and clears other bits in gpe0 enable registers. So we need to inform the kernel to keep gpio_tier_sci also set as these are needed for any wake event. This patch adds ASL code for sleep button device with HID id PNP0C0E. We are adding _PRW method for sleep button device with this patch. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16564 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/vboot/vboot_handoff.c')
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