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authorWerner Zeh <werner.zeh@siemens.com>2022-03-09 08:47:23 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-14 15:53:54 +0000
commit06fe5d565d78067bd50066a8caf51ed412b31b0a (patch)
tree8d4c770c3ed76355c674a8e09bd6696a7332df78 /src/superio
parentceecc485b0dfe5ab29cd424577fa04099117fec1 (diff)
mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/superio')
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