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authorFelix Held <felix-coreboot@felixheld.de>2020-12-09 02:16:27 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-10 01:21:53 +0000
commit1e63e361c68eda9c4876de24416880ab83ec29d9 (patch)
treeab714e1c4fa5e05f385eaf5ca77d6356e704b954 /src/superio
parent63eb64be26bfa30f1cc18d75ec98d63b3e8b4f26 (diff)
soc/amd/picasso/reset: remove leftover PCI includes
On Stoneyridge some PCI registers were accessed in this compilation unit, but on Picasso this is no longer the case. Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio')
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