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author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-08-11 18:28:29 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-24 14:05:35 +0000 |
commit | f5b3a49b76e3feeb617c51df432d36bdb043a0ce (patch) | |
tree | 856b1d18046924f39985eb4a346eb1e25928999d /src/superio | |
parent | bf4e71e1b3412d3fc864f6b1e4eda22f60c6d47d (diff) |
mb/intel/jslrvp: Correct PCI root port mapping
Jasper Lake SoC had PCI root port mapping swap, thats why we were
using swapped mapping earlier for all the boards
Recently, patch was pushed to handle this swap in PCI enumeration code
for Jasper Lake and we need to correct this mapping. Now this mapping
aligns with actual port mapping in the schematics
BUG=None
BRANCH=None
TEST=NVMe and WLAN are getting detected after this changes
Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/superio')
0 files changed, 0 insertions, 0 deletions