eric patch

        1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 333 insertions, 69 deletions

diff --git a/src/superio/NSC/pc87427/Config.lb b/src/superio/NSC/pc87427/Config.lb
new file mode 100644
index 0000000000..f62a567d61
--- /dev/null
+++ b/src/superio/NSC/pc87427/Config.lb
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
diff --git a/src/superio/NSC/pc87427/chip.h b/src/superio/NSC/pc87427/chip.h
new file mode 100644
index 0000000000..ae46971590
--- /dev/null
+++ b/src/superio/NSC/pc87427/chip.h
@@ -0,0 +1,16 @@
+#ifndef SIO_COM1
+#define SIO_COM1_BASE   0x3F8
+#endif
+#ifndef SIO_COM2
+#define SIO_COM2_BASE   0x2F8
+#endif
+
+extern struct chip_operations superio_NSC_pc87427_ops;
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct superio_NSC_pc87427_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
diff --git a/src/superio/NSC/pc87427/pc87427.h b/src/superio/NSC/pc87427/pc87427.h
new file mode 100644
index 0000000000..d998bd6c20
--- /dev/null
+++ b/src/superio/NSC/pc87427/pc87427.h
@@ -0,0 +1,94 @@
+#define PC87427_FDC  0x00 /* Floppy */
+#define PC87427_SP2  0x02 /* Com2 */
+#define PC87427_SP1  0x03 /* Com1 */
+#define PC87427_SWC  0x04
+#define PC87427_KBCM 0x05 /* Mouse */
+#define PC87427_KBCK 0x06 /* Keyboard */
+#define PC87427_GPIO 0x07
+#define PC87427_FMC  0x09
+#define PC87427_WDT  0x0A
+#define PC87427_XBUS 0x0F
+#define PC87427_RTC  0x10
+#define PC87427_MHC  0x14
+
+#define PC87427_GPIO_DEV PNP_DEV(0x2e, PC87427_GPIO)
+/* This is to get around a romcc bug */
+//#define PC87427_XBUS_DEV PNP_DEV(0x2e, PC87427_XBUS)
+#define PC87427_XBUS_DEV PNP_DEV(0x2e, 0x0f)
+
+#define PC87427_GPSEL		0xf0
+#define PC87427_GPCFG1		0xf1
+#define PC87427_GPEVR		0xf2
+#define PC87427_GPCFG2		0xf3
+#define PC87427_EXTCFG		0xf4
+#define PC87427_IOEXT1A		0xf5
+#define PC87427_IOEXT1B		0xf6
+#define PC87427_IOEXT2A		0xf7
+#define PC87427_IOEXT2B		0xf8
+
+#define PC87427_GPDO_0		0x00
+#define PC87427_GPDI_0		0x01
+#define PC87427_GPDO_1		0x02
+#define PC87427_GPDI_1		0x03
+#define PC87427_GPEVEN_1	0x04
+#define PC87427_GPEVST_1	0x05
+#define PC87427_GPDO_2		0x06
+#define PC87427_GPDI_2		0x07
+#define PC87427_GPDO_3		0x08
+#define PC87427_GPDI_3		0x09
+#define PC87427_GPDO_4		0x0a
+#define PC87427_GPDI_4		0x0b
+#define PC87427_GPEVEN_4	0x0c
+#define PC87427_GPEVST_4	0x0d
+#define PC87427_GPDO_5		0x0e
+#define PC87427_GPDI_5		0x0f
+#define PC87427_GPDO_6		0x10
+#define PC87427_GPDO_7A		0x11
+#define PC87427_GPDO_7B		0x12
+#define PC87427_GPDO_7C		0x13
+#define PC87427_GPDO_7D		0x14
+#define PC87427_GPDI_7A		0x15
+#define PC87427_GPDI_7B		0x16
+#define PC87427_GPDI_7C		0x17
+#define PC87427_GPDI_7D		0x18
+
+#define PC87427_XIOCNF		0xf0
+#define PC87427_XIOBA1H		0xf1
+#define PC87427_XIOBA1L		0xf2
+#define PC87427_XIOSIZE1	0xf3
+#define PC87427_XIOBA2H		0xf4
+#define PC87427_XIOBA2L		0xf5
+#define PC87427_XIOSIZE2	0xf6
+#define PC87427_XMEMCNF1	0xf7
+#define PC87427_XMEMCNF2	0xf8
+#define PC87427_XMEMBAH		0xf9
+#define PC87427_XMEMBAL		0xfa
+#define PC87427_XMEMSIZE	0xfb
+#define PC87427_XIRQMAP1	0xfc
+#define PC87427_XIRQMAP2	0xfd
+#define PC87427_XBIMM		0xfe
+#define PC87427_XBBSL		0xff
+
+#define PC87427_XBCNF		0x00
+#define PC87427_XZCNF0		0x01
+#define PC87427_XZCNF1		0x02
+#define PC87427_XIRQC0		0x04
+#define PC87427_XIRQC1		0x05
+#define PC87427_XIRQC2		0x06
+#define PC87427_XIMA0		0x08
+#define PC87427_XIMA1		0x09
+#define PC87427_XIMA2		0x0a
+#define PC87427_XIMA3		0x0b
+#define PC87427_XIMD		0x0c
+#define PC87427_XZCNF2		0x0d
+#define PC87427_XZCNF3		0x0e
+#define PC87427_XZM0		0x0f
+#define PC87427_XZM1		0x10
+#define PC87427_XZM2		0x11
+#define PC87427_XZM3		0x12
+#define PC87427_HAP0		0x13
+#define PC87427_HAP1		0x14
+#define PC87427_XSCNF		0x15
+#define PC87427_XWBCNF		0x16
+
+
diff --git a/src/superio/NSC/pc87427/pc87427_early_init.c b/src/superio/NSC/pc87427/pc87427_early_init.c
new file mode 100644
index 0000000000..71f702f11f
--- /dev/null
+++ b/src/superio/NSC/pc87427/pc87427_early_init.c
@@ -0,0 +1,31 @@
+#include <arch/romcc_io.h>
+#include "pc87427.h"
+
+static void pc87427_disable_dev(device_t dev)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+}
+static void pc87427_enable_dev(device_t dev, unsigned iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}
+static void xbus_cfg(device_t dev)
+{
+	uint8_t i, data;
+	uint16_t xbus_index;
+
+	pnp_set_logical_device(dev);
+	/* select proper BIOS size (4MB) */
+	pnp_write_config(dev, PC87427_XMEMCNF2, (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04);
+	xbus_index = pnp_read_iobase(dev, 0x60);
+
+	/* enable writes to devices attached to XCS0 (XBUS Chip Select 0) */
+	for (i=0; i<= 0xf; i++) {
+		outb((i<<4), xbus_index + PC87427_HAP0);
+	}
+	return; 
+}	
diff --git a/src/superio/NSC/pc87427/superio.c b/src/superio/NSC/pc87427/superio.c
new file mode 100644
index 0000000000..84c6ecb628
--- /dev/null
+++ b/src/superio/NSC/pc87427/superio.c
@@ -0,0 +1,77 @@
+/* Copyright 2000  AG Electronics Ltd. */
+/* Copyright 2003-2004 Linux Networx */
+/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include "chip.h"
+#include "pc87427.h"
+
+
+static void init(device_t dev)
+{
+	struct superio_NSC_pc87427_config *conf;
+	struct resource *res0, *res1;
+	/* Wishlist handle well known programming interfaces more
+	 * generically.
+	 */
+	if (!dev->enabled) {
+		return;
+	}
+	conf = dev->chip_info;
+	switch(dev->path.u.pnp.device) {
+	case PC87427_SP1: 
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case PC87427_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case PC87427_KBCK:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops,  PC87427_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
+ { &ops,  PC87427_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops,  PC87427_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops,  PC87427_SWC,  PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, 
+   { 0xfff0, 0 }, { 0xfffc, 0 }, { 0xfffc, 0 }, { 0xfff8, 0 } },
+ { &ops,  PC87427_KBCM, PNP_IRQ0 },
+ { &ops,  PC87427_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+ { &ops,  PC87427_GPIO, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
+ { &ops,  PC87427_WDT,  PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
+ { &ops,  PC87427_FMC,  PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
+ { &ops,  PC87427_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
+ { &ops,  PC87427_RTC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xfffe, 0 }, { 0xfffe, 0 } },
+ { &ops,  PC87427_MHC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffe0, 0 }, { 0xffe0, 0 } },
+};
+
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); 
+}
+
+struct chip_operations superio_NSC_pc87427_ops = {
+	CHIP_NAME("NSC 87427")
+	.enable_dev = enable_dev,
+};
diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c
index 5a456099c8..ab9da13e93 100644
--- a/src/superio/smsc/lpc47b397/superio.c
+++ b/src/superio/smsc/lpc47b397/superio.c
@@ -45,33 +45,6 @@ static void enable_hwm_smbus(device_t dev) {
         value |= 0x01;
         pnp_write_config(dev, reg, value);
 } 
-#if 0
-static void dump_pnp_device(device_t dev)
-{
-        int i;
-        print_debug("\r\n");
-
-        for(i = 0; i <= 255; i++) {
-                uint8_t reg, val;
-                if ((i & 0x0f) == 0) {
-                        print_debug_hex8(i);
-                        print_debug_char(':');
-                }
-		reg = i;
-		if(i!=0xaa) {
-                	val = pnp_read_config(dev, reg);
-		}
-		else {
-			val = 0xaa;
-		}
-                print_debug_char(' ');
-                print_debug_hex8(val);
-                if ((i & 0x0f) == 0x0f) {
-                        print_debug("\r\n");
-                }
-        }
-}
-#endif
 
 
 static void lpc47b397_init(device_t dev)
diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c
index 57d475b00f..559bdf1189 100644
--- a/src/superio/winbond/w83627hf/superio.c
+++ b/src/superio/winbond/w83627hf/superio.c
@@ -12,6 +12,7 @@
 #include <bitops.h>
 #include <uart8250.h>
 #include <pc80/keyboard.h>
+#include <pc80/mc146818rtc.h>
 #include "chip.h"
 #include "w83627hf.h"
 
@@ -47,33 +48,22 @@ static void enable_hwm_smbus(device_t dev) {
 	pnp_write_config(dev, reg, value);
 }
 
-#if 0
-static void dump_pnp_device(device_t dev)
+static void init_acpi(device_t dev)
 {
-        int i;
-        print_debug("\r\n");
-
-        for(i = 0; i <= 255; i++) {
-                uint8_t reg, val;
-                if ((i & 0x0f) == 0) {
-                        print_debug_hex8(i);
-                        print_debug_char(':');
-                }
-		reg = i;
-		if(i!=0xaa) {
-                	val = pnp_read_config(dev, reg);
-		}
-		else {
-			val = 0xaa;
-		}
-                print_debug_char(' ');
-                print_debug_hex8(val);
-                if ((i & 0x0f) == 0x0f) {
-                        print_debug("\r\n");
-                }
-        }
+	uint8_t  value = 0x20;
+	int power_on = 1;
+
+	get_option(&power_on, "power_on_after_fail");
+	pnp_enter_ext_func_mode(dev);
+	pnp_write_index(dev->path.u.pnp.port,7,0x0a); 
+	value = pnp_read_config(dev, 0xE4);
+	value &= ~(3<<5);
+	if(power_on) {
+		value |= (1<<5);
+	}
+	pnp_write_config(dev, 0xE4, value);
+        pnp_exit_ext_func_mode(dev);  
 }
-#endif
 
 static void init_hwm(unsigned long base)
 {
@@ -105,7 +95,6 @@ static void init_hwm(unsigned long base)
 	}
 }
 
-
 static void w83627hf_init(device_t dev)
 {
 	struct superio_winbond_w83627hf_config *conf;
@@ -133,21 +122,16 @@ static void w83627hf_init(device_t dev)
 #define HWM_INDEX_PORT 5
                 init_hwm(res0->base + HWM_INDEX_PORT);
                 break;
+        case W83627HF_ACPI:
+                init_acpi(dev);
+                break;
 	}
-	
 }
 
 void w83627hf_pnp_set_resources(device_t dev)
 {
-
 	pnp_enter_ext_func_mode(dev);  
-
 	pnp_set_resources(dev);
-
-#if 0
-        dump_pnp_device(dev);
-#endif
-                
         pnp_exit_ext_func_mode(dev);  
         
 }       
@@ -155,20 +139,13 @@ void w83627hf_pnp_set_resources(device_t dev)
 void w83627hf_pnp_enable_resources(device_t dev)
 {       
         pnp_enter_ext_func_mode(dev);  
-	
 	pnp_enable_resources(dev);               
-
         switch(dev->path.u.pnp.device) {
 	case W83627HF_HWM:
 		printk_debug("w83627hf hwm smbus enabled\n");
 		enable_hwm_smbus(dev);
 		break;
 	}
-
-#if 0  
-        dump_pnp_device(dev);
-#endif
-
         pnp_exit_ext_func_mode(dev);  
 
 }
@@ -219,4 +196,3 @@ struct chip_operations superio_winbond_w83627hf_ops = {
 	CHIP_NAME("Winbond w83627hf")
 	.enable_dev = enable_dev,
 };
-
diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h
index 0cf16310c3..7cd664cd16 100644
--- a/src/superio/winbond/w83627hf/w83627hf.h
+++ b/src/superio/winbond/w83627hf/w83627hf.h
@@ -9,3 +9,83 @@
 #define W83627HF_GPIO3            9
 #define W83627HF_ACPI            10
 #define W83627HF_HWM             11   /* Hardware Monitor */
+
+//#define W83627HF_GPIO_DEV PNP_DEV(0x2e, W83627HF_GPIO)
+//#define W83627HF_XBUS_DEV PNP_DEV(0x2e, W83627HF_XBUS)
+
+#define W83627HF_GPSEL		0xf0
+#define W83627HF_GPCFG1		0xf1
+#define W83627HF_GPEVR		0xf2
+#define W83627HF_GPCFG2		0xf3
+#define W83627HF_EXTCFG		0xf4
+#define W83627HF_IOEXT1A		0xf5
+#define W83627HF_IOEXT1B		0xf6
+#define W83627HF_IOEXT2A		0xf7
+#define W83627HF_IOEXT2B		0xf8
+
+#define W83627HF_GPDO_0		0x00
+#define W83627HF_GPDI_0		0x01
+#define W83627HF_GPDO_1		0x02
+#define W83627HF_GPDI_1		0x03
+#define W83627HF_GPEVEN_1	0x04
+#define W83627HF_GPEVST_1	0x05
+#define W83627HF_GPDO_2		0x06
+#define W83627HF_GPDI_2		0x07
+#define W83627HF_GPDO_3		0x08
+#define W83627HF_GPDI_3		0x09
+#define W83627HF_GPDO_4		0x0a
+#define W83627HF_GPDI_4		0x0b
+#define W83627HF_GPEVEN_4	0x0c
+#define W83627HF_GPEVST_4	0x0d
+#define W83627HF_GPDO_5		0x0e
+#define W83627HF_GPDI_5		0x0f
+#define W83627HF_GPDO_6		0x10
+#define W83627HF_GPDO_7A		0x11
+#define W83627HF_GPDO_7B		0x12
+#define W83627HF_GPDO_7C		0x13
+#define W83627HF_GPDO_7D		0x14
+#define W83627HF_GPDI_7A		0x15
+#define W83627HF_GPDI_7B		0x16
+#define W83627HF_GPDI_7C		0x17
+#define W83627HF_GPDI_7D		0x18
+
+#define W83627HF_XIOCNF		0xf0
+#define W83627HF_XIOBA1H		0xf1
+#define W83627HF_XIOBA1L		0xf2
+#define W83627HF_XIOSIZE1	0xf3
+#define W83627HF_XIOBA2H		0xf4
+#define W83627HF_XIOBA2L		0xf5
+#define W83627HF_XIOSIZE2	0xf6
+#define W83627HF_XMEMCNF1	0xf7
+#define W83627HF_XMEMCNF2	0xf8
+#define W83627HF_XMEMBAH		0xf9
+#define W83627HF_XMEMBAL		0xfa
+#define W83627HF_XMEMSIZE	0xfb
+#define W83627HF_XIRQMAP1	0xfc
+#define W83627HF_XIRQMAP2	0xfd
+#define W83627HF_XBIMM		0xfe
+#define W83627HF_XBBSL		0xff
+
+#define W83627HF_XBCNF		0x00
+#define W83627HF_XZCNF0		0x01
+#define W83627HF_XZCNF1		0x02
+#define W83627HF_XIRQC0		0x04
+#define W83627HF_XIRQC1		0x05
+#define W83627HF_XIRQC2		0x06
+#define W83627HF_XIMA0		0x08
+#define W83627HF_XIMA1		0x09
+#define W83627HF_XIMA2		0x0a
+#define W83627HF_XIMA3		0x0b
+#define W83627HF_XIMD		0x0c
+#define W83627HF_XZCNF2		0x0d
+#define W83627HF_XZCNF3		0x0e
+#define W83627HF_XZM0		0x0f
+#define W83627HF_XZM1		0x10
+#define W83627HF_XZM2		0x11
+#define W83627HF_XZM3		0x12
+#define W83627HF_HAP0		0x13
+#define W83627HF_HAP1		0x14
+#define W83627HF_XSCNF		0x15
+#define W83627HF_XWBCNF		0x16
+
+
diff --git a/src/superio/winbond/w83627hf/w83627hf_early_init.c b/src/superio/winbond/w83627hf/w83627hf_early_init.c
new file mode 100644
index 0000000000..e449c4ae9c
--- /dev/null
+++ b/src/superio/winbond/w83627hf/w83627hf_early_init.c
@@ -0,0 +1,15 @@
+#include <arch/romcc_io.h>
+#include "w83627hf.h"
+
+static void w83627hf_disable_dev(device_t dev)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+}
+static void w83627hf_enable_dev(device_t dev, unsigned iobase)
+{
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+}