siemens/mc_apl3: Disable CLKREQ of PCIe root ports

All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".

Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

0 files changed, 0 insertions, 0 deletions