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author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-09-08 09:56:21 +0300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-21 08:09:05 +0000 |
commit | 0f9c8b3aa5f27a619fe643156606034fcdfb2eaa (patch) | |
tree | 66252457cb95096ed1db553022eea948a06e9640 /src/superio/winbond/w83977tf/w83977tf.h | |
parent | f8c147431e6207b9f3508a7da202fe6dfb04e5a4 (diff) |
mb/razer/blade_stealth_kbl: 2/3 Exclude fields to match PAD_CFG
This patch excludes bit fields that must be ignored (1,2) in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:
./intelp2m -fld cb -ign -t 1 -file ../../src/mainboard/razer/
blade_stealth_kbl/gpio.h
- ignore RO bit fields;
- ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
Disable (bit 9:8) for the native function, because it does not
affect the pad in this mode.
This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG
Change-Id: Ia36c5d0cd449a32d76351a87a33a55196ae78443
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43858
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/winbond/w83977tf/w83977tf.h')
0 files changed, 0 insertions, 0 deletions