Add support for the Winbond W83627UHG Super I/O.

Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 176 insertions, 0 deletions

diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c
new file mode 100644
index 0000000000..796b20a8dc
--- /dev/null
+++ b/src/superio/winbond/w83627uhg/superio.c
@@ -0,0 +1,176 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Dynon Avionics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 $
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "w83627uhg.h"
+
+static void w83627uhg_enter_ext_func_mode(device_t dev)
+{
+	outb(0x87, dev->path.u.pnp.port);
+	outb(0x87, dev->path.u.pnp.port);
+}
+
+static void w83627uhg_exit_ext_func_mode(device_t dev)
+{
+	outb(0xaa, dev->path.u.pnp.port);
+}
+
+/*
+ * Set the UART clock source.
+ *
+ * Possible UART clock source speeds are:
+ *
+ *   0 = 1.8462 MHz (default)
+ *   1 = 2 MHz
+ *   2 = 24 MHz
+ *   3 = 14.769 MHz
+ *
+ * The faster clocks allow for BAUD rates up to 2mbits.
+ *
+ * Warning: The kernel will need to be adjusted since it assumes
+ * a 1.8462 MHz clock.
+ */
+static void set_uart_clock_source(device_t dev, u8 uart_clock)
+{
+	u8 value;
+
+	w83627uhg_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	value = pnp_read_config(dev, 0xf0);
+	value &= ~0x03;
+	value |= (uart_clock & 0x03);
+	pnp_write_config(dev, 0xf0, value);
+	w83627uhg_exit_ext_func_mode(dev);
+}
+
+static void w83627uhg_init(device_t dev)
+{
+	struct superio_winbond_w83627uhg_config *conf;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled)
+		return;
+
+	conf = dev->chip_info;
+	switch(dev->path.u.pnp.device) {
+	case W83627UHG_SP1: 
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		/* set_uart_clock_source(dev, 0); */
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case W83627UHG_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		/* set_uart_clock_source(dev, 0); */
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case W83627UHG_SP3:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		/* set_uart_clock_source(dev, 0); */
+		init_uart8250(res0->base, &conf->com3);
+		break;
+	case W83627UHG_SP4:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		/* set_uart_clock_source(dev, 0); */
+		init_uart8250(res0->base, &conf->com4);
+		break;
+	case W83627UHG_SP5:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		/* set_uart_clock_source(dev, 0); */
+		init_uart8250(res0->base, &conf->com5);
+		break;
+	case W83627UHG_SP6:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		/* set_uart_clock_source(dev, 0); */
+		init_uart8250(res0->base, &conf->com6);
+		break;
+	case W83627UHG_KBC:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		res1 = find_resource(dev, PNP_IDX_IO1);
+		init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+		break;
+	}
+}
+
+static void w83627uhg_set_resources(device_t dev)
+{
+	w83627uhg_enter_ext_func_mode(dev);
+	pnp_set_resources(dev);
+	w83627uhg_exit_ext_func_mode(dev);
+}
+
+static void w83627uhg_enable_resources(device_t dev)
+{
+	w83627uhg_enter_ext_func_mode(dev);
+	pnp_enable_resources(dev);
+	w83627uhg_exit_ext_func_mode(dev);
+}
+
+static void w83627uhg_enable(device_t dev)
+{
+	w83627uhg_enter_ext_func_mode(dev);
+	pnp_enable(dev);
+	w83627uhg_exit_ext_func_mode(dev);
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = w83627uhg_set_resources,
+	.enable_resources = w83627uhg_enable_resources,
+	.enable           = w83627uhg_enable,
+	.init             = w83627uhg_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+	{ &ops, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+	{ &ops, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627UHG_GPIO3_4, },
+	{ &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
+	{ &ops, W83627UHG_GPIO1_2,},
+	{ &ops, W83627UHG_ACPI, PNP_IRQ0,  },
+	{ &ops, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
+	{ &ops, W83627UHG_PECI_SST,},
+	{ &ops, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_winbond_w83627uhg_ops = {
+	CHIP_NAME("Winbond W83627UHG Super I/O")
+	.enable_dev = enable_dev,
+};