soc/intel/apollolake: enable cache-as-ram paging for glk

Add support and enalbe cache-as-ram paging for glk to work around
a cache-as-ram corruption issue. glk executes verstage, romstage,
and FSP-M directly out of cache-as-ram (just like apl). However,
the front end on glk is very agressive about pulling cache lines
into L1I for potential execution. When the snoops hit in the L1D
and the cache lines are dirty the processor writes the line back.
However, there is no backing store for the dirty lines to go. As
such when the line is pulled back in the value is all 0xff's,
corrupting cache-as-ram.

To fix the issue one needs to enable paging with NX (no execute)
permissions which prevents the above actions from happening because
the TLB will indicate that shouldn't be fetched into the instruction
cache since data will be marked no execute.

The generated page tables are added to cbfs and only added to the
COREBOOT cbfs as they are only consumed in the early cache-as-ram
stages.

The page tables generated with:

$ go run util/x86/x86_page_tables.go \
  --iomap_file=src/soc/intel/apollolake/glk_page_map.txt \
  --metadata_base_address=0xfef00000 \
  --pdpt_output_c_file=src/soc/intel/apollolake/pdpt.c \
  --pt_output_c_file=src/soc/intel/apollolake/pt.c

Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB    : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 WB NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP    : 8 big 0 small

Total Pages of page tables: 5

Pages linked using base address of 0xfef00000.

BUG=b:72728953

Change-Id: Icde9cc0bf5079bb5821f4e59eb61e939c13d7062
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

0 files changed, 0 insertions, 0 deletions