diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-11-20 17:23:39 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-04 10:20:23 +0000 |
| commit | e68042f0210738c6c8c15fc2b330801db14d7f22 (patch) | |
| tree | 9cbc24235977f26c338cb60100a069f49a14642d /src/superio/smsc | |
| parent | 84227611d5c06d1482097df6f954b03fa3043a74 (diff) | |
soc/intel/cannonlake: Add DPTF ACPI code
Define the constants that DPTF expects from the SOC in order to
use the common DPTF ACPI code. For cannonlake this indicates
the CPU device is called B0D4 and is at PCI address 00:04.0.
Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29759
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/smsc')
0 files changed, 0 insertions, 0 deletions