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author | Zheng Bao <fishbaozi@gmail.com> | 2023-02-11 15:17:22 +0800 |
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committer | Martin L Roth <gaumless@gmail.com> | 2023-09-26 16:20:45 +0000 |
commit | 1a0c99f55d57f0aeec69d1cd2ffa134a7a9ff255 (patch) | |
tree | 015f35f802aee97788c499f2ed6894cad6627dab /src/superio/smsc/lpc47n207 | |
parent | 42f8b59c119309c49b8153dcedec19674ef7f435 (diff) |
amdfwtool: Support firmware offsets of larger than 16MiB
The mapped windows is up to 16M. Even if the flash size is 32MB, it is
not mapped at 0xFE000000.
So using "0xFFFFFFFF - rom_size + 1" to get the "rom_base_address" can
only explain well when rom_size is less or equal to 16MB. For larger
size, it is not physically correct (Even though it can get expected
result).
If the flash size is larger than 16M, we assume the given addresses
are already relative ones. So we don't need the physical base address
any more.
This commit is part of a series of patches to support 32/64M flash.
BUG=b:255374782
Change-Id: I9eea45f0be45a959c4150030e7e213923510ad68
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/superio/smsc/lpc47n207')
0 files changed, 0 insertions, 0 deletions