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| author | Vadim Bendebury <vbendeb@chromium.org> | 2012-06-19 12:56:57 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-07-24 22:15:19 +0200 |
| commit | 537b4e09e644107ed644cd88f8a7fd488406b9a2 (patch) | |
| tree | 92b1fc622e2f89c55149064396459ac362f2be17 /src/superio/smsc/lpc47m10x | |
| parent | ef6b08cc486e5d97103211dfeb3d629552a92e43 (diff) | |
Add code to read Intel microcode from CBFS
When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in
CBFS and pass it to intel_update_microcode() instead of using the
compiled in array.
CBFS accesses in pre-RAM and 'normal' environments are provided
through different API.
Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1296
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/superio/smsc/lpc47m10x')
0 files changed, 0 insertions, 0 deletions