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authorThejaswani Putta <thejaswani.putta@intel.com>2019-08-28 16:23:20 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-09-19 09:35:51 +0000
commit7140db475181722163cea0b4cfce9f12b39506ee (patch)
treedc556e5e6b5f01a901d205d8afc57dd3a93a829e /src/superio/smsc/lpc47b397
parentecea91679f3193b308eabcd5f1f82525f0f5669f (diff)
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/superio/smsc/lpc47b397')
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