eric patch

        1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 0 insertions, 27 deletions

diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c
index 5a456099c8..ab9da13e93 100644
--- a/src/superio/smsc/lpc47b397/superio.c
+++ b/src/superio/smsc/lpc47b397/superio.c
@@ -45,33 +45,6 @@ static void enable_hwm_smbus(device_t dev) {
         value |= 0x01;
         pnp_write_config(dev, reg, value);
 } 
-#if 0
-static void dump_pnp_device(device_t dev)
-{
-        int i;
-        print_debug("\r\n");
-
-        for(i = 0; i <= 255; i++) {
-                uint8_t reg, val;
-                if ((i & 0x0f) == 0) {
-                        print_debug_hex8(i);
-                        print_debug_char(':');
-                }
-		reg = i;
-		if(i!=0xaa) {
-                	val = pnp_read_config(dev, reg);
-		}
-		else {
-			val = 0xaa;
-		}
-                print_debug_char(' ');
-                print_debug_hex8(val);
-                if ((i & 0x0f) == 0x0f) {
-                        print_debug("\r\n");
-                }
-        }
-}
-#endif
 
 
 static void lpc47b397_init(device_t dev)