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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-08-11 18:38:38 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-22 17:35:38 +0000
commitfbf1018805d108ea59ea000fec459e5a44110d7a (patch)
treeb95e78d48481ea230ea2f9cabef4e870501af75e /src/superio/serverengines
parentf7cd2f5b940aabb79a2ed83cdbbb4fe311e04bff (diff)
soc/intel/skylake: Lock sideband access in coreboot and not in FSP
The Sideband Acces locking code is skipped from FSP by setting an FSP-S UPD called PchSbAccessUnlock. This locking is being done in coreboot during finalize.c. This is done because coreboot was failing to disable HECI1 device using Sideband interface during finalize.c if FSP already locks the Sideband access mechanism before that. So, as a solution, coreboot passes an UPD to skip the locking in FSP, and in finalize.c, after disabling HECI, it removes the Sideband access. BUG=b:63877089 BRANCH=none TEST=Build and boot poppy to check lspci not showing Intel ME controller in the PCI device list. Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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