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authorMario Scheithauer <mario.scheithauer@siemens.com>2023-04-04 13:35:38 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-04-26 12:08:07 +0000
commit26ad42572862ca7dbcc541c60d579e14d69a0980 (patch)
tree88f6f8e727871ab0114663c304ad3eec3721c273 /src/superio/nuvoton
parentae5852bd7b0f597816b36e36d6c4d9cfe03f1af1 (diff)
mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to '0'. On this mainboard NC FPGA is connected to PCIe root port #1 (00:1c.0). Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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