soc/intel/cannonlake: Force LPC IO decode settings

Force PCH LPC generic IO ranges are identical between PCH LPC pci config
space and DMI PCR registers. Reference documentation from 570374 chapter
2.4.1.

Bug=77944335
TEST=Boot up in OS in meowth board, using iotools to read LPC pci
config space offset 0x84~0x90 and compare with values read from DMI PCR
private register offset 0x2730~0x273c are identical.

Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25668
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions