summaryrefslogtreecommitdiff
path: root/src/superio/nuvoton
diff options
context:
space:
mode:
authorBill XIE <persmule@hardenedlinux.org>2021-08-28 14:59:04 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-08-29 16:41:12 +0000
commita11eca149a0aa4d4adb6ef3091c5c4662e10af66 (patch)
tree644d5e5d0d24c230bce4848bae070968d3cb134a /src/superio/nuvoton
parentf3c84024b18239bacef6ed30923fe68ac44c0749 (diff)
superio/nuvoton/nct6776: Correct the definition of NCT6776_GPIOBASE
NCT6776's data sheet does say that the virtual LDN of GPIO base should be 0x308, and most mainboards using it usually correctly config it in devicetree.cb under the path 2e.308, but in nct6776.h it used to be defined as 8 from the beginning (an ancient commit 1e3a22649a9, lately revived in commit f95daa510d6), identical to the LDN of WDT, which eliminates the definition of value 2e.308, and makes related resource allocations unable to take effect. (in log we can find "PNP: 002e.308 missing read_resources" if 2e.308 is enabled and assigned with resources) In this commit, NCT6776_GPIOBASE is set to a value consistent with the data sheet. With this commit, resources under 2e.308 of NCT6776 can be allocated successfully. Change-Id: I604bad7ab34a8f57262fdec508e5952cf8eabf1c Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/superio/nuvoton')
-rw-r--r--src/superio/nuvoton/nct6776/nct6776.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h
index 6cab79306f..36b5d8231a 100644
--- a/src/superio/nuvoton/nct6776/nct6776.h
+++ b/src/superio/nuvoton/nct6776/nct6776.h
@@ -27,7 +27,7 @@
/* virtual LDN for GPIO and WDT */
#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V)
-#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //?
+#define NCT6776_GPIOBASE ((3 << 8) | NCT6776_WDT1_GPIO01A_V)
#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V)
#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V)