diff options
| author | Samuel Holland <samuel@sholland.org> | 2017-06-06 22:55:01 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-13 15:21:58 +0200 |
| commit | 7daac912367c4b308038ae56f78c0a07e8a03082 (patch) | |
| tree | 24e70aa5e3beadc942c7aab9c76120d6a6d943e9 /src/superio/nuvoton/nct6791d | |
| parent | c21ba2cd3e6af194cc4d933d4f7bd434dfb2ff04 (diff) | |
device/pnp: remove struct io_info
The 'set' field was not used anywhere. Replace the struct with a simple
integer representing the mask.
initializer updates performed with:
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \
src/ec/*/*/ec.c
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \
src/ec/*/*/ec_lpc.c \
src/superio/*/*/superio.c \
src/superio/smsc/fdc37n972/fdc37n972.c \
src/superio/smsc/sio10n268/sio10n268.c \
src/superio/via/vt1211/vt1211.c
src/ec/kontron/it8516e/ec.c was manually updated. The previous value for
IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and
had a zero bit in the middle of the mask.
Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/superio/nuvoton/nct6791d')
| -rw-r--r-- | src/superio/nuvoton/nct6791d/superio.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index f0da0367e2..f66689eb56 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -51,27 +51,27 @@ static struct device_operations ops = { static struct pnp_info pnp_dev_info[] = { { &ops, NCT6791D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, - {0x0ff8, 0}, }, + 0x0ff8, }, { &ops, NCT6791D_SP1, PNP_IO0 | PNP_IRQ0, - {0x0ff8, 0}, }, + 0x0ff8, }, { &ops, NCT6791D_SP2, PNP_IO0 | PNP_IRQ0, - {0x0ff8, 0}, }, + 0x0ff8, }, { &ops, NCT6791D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, - {0x0fff, 0}, {0x0fff, 4}, }, + 0x0fff, 0x0fff, }, { &ops, NCT6791D_CIR, PNP_IO0 | PNP_IRQ0, - {0x0ff8, 0}, }, + 0x0ff8, }, { &ops, NCT6791D_ACPI}, { &ops, NCT6791D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, - {0x0ffe, 0}, {0x0ffe, 4}, }, + 0x0ffe, 0x0ffe, }, { &ops, NCT6791D_BCLK_WDT2_WDTMEM}, { &ops, NCT6791D_CIRWUP, PNP_IO0 | PNP_IRQ0, - {0x0ff8, 0}, }, + 0x0ff8, }, { &ops, NCT6791D_GPIO_PP_OD}, { &ops, NCT6791D_PORT80}, { &ops, NCT6791D_WDT1}, { &ops, NCT6791D_WDTMEM}, { &ops, NCT6791D_GPIOBASE, PNP_IO0, - {0x0ff8, 0}, }, + 0x0ff8, }, { &ops, NCT6791D_GPIO0}, { &ops, NCT6791D_GPIO1}, { &ops, NCT6791D_GPIO2}, |