diff options
| author | Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> | 2019-10-07 11:59:11 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-20 11:09:57 +0000 |
| commit | 79d7f6b5fc62964e8c935b044a434ee112160059 (patch) | |
| tree | dee3c77ab9c68317b5239eaa455d0d19d5d8ae57 /src/superio/nuvoton/nct5104d/nct5104d.h | |
| parent | aa1eff30313ae325e81eeff1bc49cbfe589aff3f (diff) | |
superio/nuvoton/nct5104d: Add virtual LDN for simple GPIO IO control
Now, Super I/O GPIOs can also be controlled directly through
access to I/O registers. VLDN 108 and specific I/O port from a range
<100h; ff8h> may be enabled in mainboard devicetree.
Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/nuvoton/nct5104d/nct5104d.h')
| -rw-r--r-- | src/superio/nuvoton/nct5104d/nct5104d.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index 9a881059c0..3f78c1d0d4 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -40,7 +40,6 @@ #define NCT5104D_FDC 0x00 /* FDC - not pinned out */ #define NCT5104D_SP1 0x02 /* UARTA */ #define NCT5104D_SP2 0x03 /* UARTB */ -#define NCT5104D_GPIO_WDT 0x08 /* GPIO WDT Interface */ #define NCT5104D_GPIO_PP_OD 0x0F /* GPIO Push-Pull / Open drain select */ #define NCT5104D_SP3 0x10 /* UARTC */ #define NCT5104D_SP4 0x11 /* UARTD */ @@ -48,6 +47,7 @@ /* Virtual Logical Device Numbers (LDN) */ #define NCT5104D_GPIO_V 0x07 /* GPIO - 0,1,6 Interface */ +#define NCT5104D_GPIO_WDT_V 0x08 /* GPIO/WDT Interface */ /* Virtual devices sharing the enables are encoded as follows: VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN @@ -56,6 +56,9 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) +#define NCT5104D_GPIO_WDT ((0 << 8) | NCT5104D_GPIO_WDT_V) +#define NCT5104D_GPIO_IO ((1 << 8) | NCT5104D_GPIO_WDT_V) + void nct5104d_enable_uartd(pnp_devfn_t dev); #endif /* SUPERIO_NUVOTON_NCT5104D_H */ |