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authorJan Philipp Groß <jeangrande@mailbox.org>2024-06-04 20:54:50 +0200
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2024-07-02 15:09:40 +0000
commite52ccf2db09304e36c538bf0116e54fe484d96f6 (patch)
tree2ac5398015b52b5c6154a6cc6c366506cf04beb2 /src/superio/ite/it8772f
parent7784e099fb5a96a8f19a4a04770b825ea089cda5 (diff)
mb/asrock: Add Z87M OC Formula (Haswell)
This port was done via autoport and subsequent manual tweaking. Special thanks to Nicholas Chin! This port would have never succeeded without his help. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection switch and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - USB 2.0 Ports - Vertical Type A USB 2.0 - USB 3.1 Gen1 Ports - HD Audio Jack (audio output) - Front panel audio connector (audio output) - RJ-45 Gigabit LAN Port - SATA3 6.0 Gb/s connectors - mSATA/mini-PCI Express slot - half mini-PCI Express slot - PCI Express 3.0 x16 slots (both) - PCI Express 2.0 x4 slot - PCI Express 2.0 x1 slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection Switch - Slow Mode Switch (locks the CPU at 800MHz) not (yet) tested: - IR header - COM Port header - Power LED header - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - Optical SPDIF Out Port not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. - Post Status Checker (PSC) Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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