diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-09 20:26:25 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-10-27 12:50:33 +0100 |
| commit | 85836c2215498ff18746b3a7e85ed684cf2e119e (patch) | |
| tree | 1b774a8f00fda2e0ccc1939105e5f4f2c7c8abe3 /src/superio/ite/it8772f/early_init.c | |
| parent | 377fd754932922e8c907994ef3e4d8ab925c6132 (diff) | |
superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
The romstage component of Super I/O support is in fact written around
passing a lower and upper half packed integer. We currently have two
typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of
'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the
ramstage context and so is really a conflicting definition. This helps
solve problems down the road to having the 'real' 'device_t' definition
usable in romstage later.
This follows on from the rational given in:
c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6231
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/superio/ite/it8772f/early_init.c')
| -rw-r--r-- | src/superio/ite/it8772f/early_init.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index 1ae80c8294..55e06f74b9 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -26,8 +26,8 @@ /* NOTICE: This file is deprecated, use ite/common instead */ /* RAMstage equiv */ -/* u8 pnp_read_config(device_t dev, u8 reg) */ -u8 it8772f_sio_read(device_t dev, u8 reg) +/* u8 pnp_read_config(pnp_devfn_t dev, u8 reg) */ +u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg) { u16 port = dev >> 8; @@ -36,8 +36,8 @@ u8 it8772f_sio_read(device_t dev, u8 reg) } /* RAMstage equiv */ -/* void pnp_write_config(device_t dev, u8 reg, u8 value) */ -void it8772f_sio_write(device_t dev, u8 reg, u8 value) +/* void pnp_write_config(pnp_devfn_t dev, u8 reg, u8 value) */ +void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value) { u16 port = dev >> 8; @@ -45,7 +45,7 @@ void it8772f_sio_write(device_t dev, u8 reg, u8 value) outb(value, port + 1); } -void it8772f_enter_conf(device_t dev) +void it8772f_enter_conf(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -55,13 +55,13 @@ void it8772f_enter_conf(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -void it8772f_exit_conf(device_t dev) +void it8772f_exit_conf(pnp_devfn_t dev) { it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02); } /* Set AC resume to be up to the Southbridge */ -void it8772f_ac_resume_southbridge(device_t dev) +void it8772f_ac_resume_southbridge(pnp_devfn_t dev) { it8772f_enter_conf(dev); it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); @@ -70,7 +70,7 @@ void it8772f_ac_resume_southbridge(device_t dev) } /* Configure a set of GPIOs */ -void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, +void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable) { set--; /* Set 1 is offset 0 */ |