diff options
author | Shelley Chen <shchen@google.com> | 2021-10-07 23:09:36 -0700 |
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committer | Shelley Chen <shchen@google.com> | 2021-10-15 15:38:34 +0000 |
commit | 9573c0ed3adbca869cf1b88312a10cc72b756547 (patch) | |
tree | 97c2d144f428195d2e3368eb9b56bc055fcd5ab5 /src/superio/ite/it8728f/Makefile.inc | |
parent | ad6f87d61202984e7604a35b6ce5babee614e676 (diff) |
soc/qualcomm/sc7280: Enable compression of SHRM
The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
Also, did some cleanup in this file based on comments in CB:49392.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/superio/ite/it8728f/Makefile.inc')
0 files changed, 0 insertions, 0 deletions