diff options
| author | Joel Linn <jl@conductive.de> | 2024-03-29 14:08:35 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2024-04-13 13:22:58 +0000 |
| commit | fb51661be11f4372f016b2c117114ceec574a2be (patch) | |
| tree | d47f3c16b4e5af4581bc7f4c1ac5eec8cbeec598 /src/superio/ite/common | |
| parent | 1a7ffa8521e0cee15a689176b29048e1c2bfcbcf (diff) | |
superio/ite: Unify it8772f with common code
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.
The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.
Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/superio/ite/common')
| -rw-r--r-- | src/superio/ite/common/early_serial.c | 21 | ||||
| -rw-r--r-- | src/superio/ite/common/ite.h | 1 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 5ff403f497..552f1104ba 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -15,6 +15,7 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ #define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */ #define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */ +#define ITE_CONFIG_REG_APC_PME_CTL2 0xf4 /* APC_PME Control 2 */ /* Helper procedure */ static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) @@ -136,3 +137,23 @@ void ite_kill_watchdog(pnp_devfn_t dev) ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00); pnp_exit_conf_state(dev); } + +/* + * Set AC resume to be up to the Southbridge + * pass EC_DEV + */ +void ite_ac_resume_southbridge(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL2); + /* + * Set both + * 6: Gate Extra PWRON# Pulse + * 5: PSON# state when 3VSB switched to on + */ + tmp |= 0x60; + pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL2, tmp); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 3e9b50289a..19ade4b9b6 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -17,6 +17,7 @@ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); void ite_enable_3vsbsw(pnp_devfn_t dev); void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); +void ite_ac_resume_southbridge(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); |