diff options
| author | Vagiz Trakhanov <rakkin@autistici.org> | 2017-09-28 14:21:54 +0000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-22 02:19:15 +0000 |
| commit | 17c577153042b6559bf7a9dca6ae9f644b18d770 (patch) | |
| tree | ee9c3c2381a73e6b9c7d36521a1af1c99aa2c6ac /src/superio/ite/common/env_ctrl.h | |
| parent | c85890d0d8887462e72837c3ae6dd5b6842a81cb (diff) | |
superio/ite/common: Add temperature offset
Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.
As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.
I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.
TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/superio/ite/common/env_ctrl.h')
| -rw-r--r-- | src/superio/ite/common/env_ctrl.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index fa131166c0..1be6436310 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -93,6 +93,26 @@ #define ITE_EC_ADC_TEMP_DIODE_MODE(x) (1 << ((x)-1)) #define ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE 0x55 +/* Matches length of ITE_EC_TMPIN_CNT */ +static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; + +#define ITE_EC_BEEP_ENABLE 0x5C +#define ITE_EC_TEMP_ADJUST_WRITE_ENABLE (1 << 7) +#define ITE_EC_ADC_CLOCK_1MHZ (6 << 4) +#define ITE_EC_ADC_CLOCK_2MHZ (7 << 4) +#define ITE_EC_ADC_CLOCK_24MHZ (5 << 4) +#define ITE_EC_ADC_CLOCK_31KHZ (4 << 4) +#define ITE_EC_ADC_CLOCK_62KHZ (3 << 4) +#define ITE_EC_ADC_CLOCK_125KHZ (2 << 4) +#define ITE_EC_ADC_CLOCK_250KHZ (1 << 4) +#define ITE_EC_ADC_CLOCK_500KHZ (0 << 4) +#define ITE_EC_BEEP_ON_TMP_LIMIT (1 << 2) +#define ITE_EC_BEEP_ON_VIN_LIMIT (1 << 1) +#define ITE_EC_BEEP_ON_FAN_LIMIT (1 << 0) +#define ITE_EC_BEEP_FREQ_DIV_OF_FAN 0x5D +#define ITE_EC_BEEP_FREQ_DIV_OF_VOLT 0x5E +#define ITE_EC_BEEP_FREQ_DIV_OF_TEMP 0x5F + #define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) (0x60 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) (0x61 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) (0x62 + ((x)-1) * 8) |