C and other Super I/O cosmetic fixes.

 - Random coding style, whitespace and cosmetic fixes.
 
 - Consistently use the same spacing and 4-hexdigit port number format
   in the pnp_dev_info[] arrays.
 
 - Drop dead/unused code and less useful comments.
 
 - Add missing "(C)" characters and copyright years.
 
 - Shorten and simplify some code snippets.
 
 - Use u8/u16/etc. everywhere.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 33 insertions, 34 deletions

diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c
index 8a5d3abec9..e1012bae51 100644
--- a/src/superio/fintek/f71805f/superio.c
+++ b/src/superio/fintek/f71805f/superio.c
@@ -90,12 +90,12 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
-	{ &ops, F71805F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &ops, F71805F_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71805F_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71805F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
-	{ &ops, F71805F_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
+	/* TODO: Some of the 0x07f8 etc. values may not be correct. */
+	{ &ops, F71805F_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71805F_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71805F_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71805F_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71805F_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
 	{ &ops, F71805F_GPIO, PNP_IRQ0, },
 	{ &ops, F71805F_PME, },
 };
diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c
index 445f66a6b5..d7d71c6ec8 100755
--- a/src/superio/fintek/f71859/superio.c
+++ b/src/superio/fintek/f71859/superio.c
@@ -87,9 +87,8 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
-	{ &ops, F71859_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-
+	/* TODO: Some of the 0x07f8 etc. values may not be correct. */
+	{ &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 };
 
 static void enable_dev(device_t dev)
diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c
index ccfde171a6..f54d3ad22b 100644
--- a/src/superio/fintek/f71863fg/superio.c
+++ b/src/superio/fintek/f71863fg/superio.c
@@ -94,15 +94,15 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
-	{ &ops, F71863FG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-	{ &ops, F71863FG_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71863FG_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71863FG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-	{ &ops, F71863FG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
-	{ &ops, F71863FG_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
-	{ &ops, F71863FG_GPIO, },
-	{ &ops, F71863FG_VID,  PNP_IO0, { 0x07f8, 0 }, },
+	/* TODO: Some of the 0x07f8 etc. values may not be correct. */
+	{ &ops, F71863FG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71863FG_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71863FG_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71863FG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71863FG_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, F71863FG_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
+	{ &ops, F71863FG_GPIO, }
+	{ &ops, F71863FG_VID,  PNP_IO0, {0x07f8, 0}, },
 	{ &ops, F71863FG_SPI, },
 	{ &ops, F71863FG_PME, },
 };
diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c
index 764dc541d3..f1a27e470d 100644
--- a/src/superio/fintek/f71872/superio.c
+++ b/src/superio/fintek/f71872/superio.c
@@ -92,15 +92,15 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
-	{ &ops, F71872_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-	{ &ops, F71872_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71872_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71872_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-	{ &ops, F71872_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
-	{ &ops, F71872_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0 }, },
+	/* TODO: Some of the 0x07f8 etc. values may not be correct. */
+	{ &ops, F71872_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71872_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71872_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71872_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71872_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, F71872_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
 	{ &ops, F71872_GPIO, PNP_IRQ0, },
-	{ &ops, F71872_VID,  PNP_IO0, { 0x0ff8, 0 }, },
+	{ &ops, F71872_VID,  PNP_IO0, {0x0ff8, 0}, },
 	{ &ops, F71872_PM, },
 };
 
diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c
index 9b5847a9e0..b26b41133d 100644
--- a/src/superio/fintek/f71889/superio.c
+++ b/src/superio/fintek/f71889/superio.c
@@ -93,15 +93,15 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
-	{ &ops, F71889_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-	{ &ops, F71889_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71889_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	{ &ops, F71889_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
-	{ &ops, F71889_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
-	{ &ops, F71889_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
+	/* TODO: Some of the 0x07f8 etc. values may not be correct. */
+	{ &ops, F71889_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71889_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71889_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, F71889_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, F71889_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, F71889_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
 	{ &ops, F71889_GPIO, },
-	{ &ops, F71889_VID,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
+	{ &ops, F71889_VID,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, F71889_SPI, },
 	{ &ops, F71889_PME, },
 	{ &ops, F71889_VREF, },