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authorYidi Lin <yidilin@chromium.org>2024-08-27 13:19:35 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-09-02 09:03:36 +0000
commit7c71b9498446ca45ac3b00af1c07eddfa5b89930 (patch)
tree57d1a77aa4ff6ab55097b6c010137f20531b2959 /src/superio/fintek
parentd86c5bf83b66565c437b0c3f399c61305c33d870 (diff)
soc/mediatek/common/pcie: Use clr/setbits32p
Use clr/setbits32p to make code cleaner. BUG=none TEST=emerge-cherry coreboot Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Diffstat (limited to 'src/superio/fintek')
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