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authorAamir Bohra <aamir.bohra@intel.com>2018-12-16 13:10:58 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-12-23 05:12:14 +0000
commit4b85d46170ef44ab88b9cf844e3d3feaf9e7e89e (patch)
tree23405bc1cbb8224ed4043e5a90a837b4966ea633 /src/superio/fintek/f81866d
parent09e7b998379225fb0b79e5fd2fb5ba9b95bd6961 (diff)
mb/google/hatch: Add memory init setup for hatch
This implementation adds below support: 1. Add support to read memory strap. 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include SPD configuration BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30248 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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