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authorAngel Pons <th3fanbus@gmail.com>2020-08-04 19:22:01 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-07 11:56:29 +0000
commit2f1739ada8a32a70dbd5a3fd1a3d6fd5fba6d291 (patch)
tree9dffa1ffb9d10b34600344fddca6cfba19d8c0d2 /src/superio/fintek/f81865f/superio.c
parentbf9bc50ec1d1b54a9ae0b86fc1e37e013422186f (diff)
security/intel/txt: Fix variable MTRR handling
The MSR macros were treated as memory addresses and the loops had off-by-one errors. This resulted in a CPU exception before GETSEC, and another exception after GETSEC (once the first exception was fixed). Tested on Asrock B85M Pro4, ACM complains about the missing TPM and resets the platform. When the `getsec` instruction is commented-out, the board is able to boot normally, without any exceptions nor corruption. Change-Id: Ib5d23cf9885401f3ec69b0f14cea7bad77eee19a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/superio/fintek/f81865f/superio.c')
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