Add support for Fintek F71872 superio.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 252 insertions, 0 deletions

diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc
new file mode 100644
index 0000000000..d7cd998caf
--- /dev/null
+++ b/src/superio/fintek/f71872/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c
diff --git a/src/superio/fintek/f71872/chip.h b/src/superio/fintek/f71872/chip.h
new file mode 100644
index 0000000000..6625711a68
--- /dev/null
+++ b/src/superio/fintek/f71872/chip.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F71872_CHIP_H
+#define SUPERIO_FINTEK_F71872_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_fintek_f71872_ops;
+
+struct superio_fintek_f71872_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif
diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h
new file mode 100644
index 0000000000..5b9b3535ba
--- /dev/null
+++ b/src/superio/fintek/f71872/f71872.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F71872_F71872_H
+#define SUPERIO_FINTEK_F71872_F71872_H
+
+/* Logical Device Numbers (LDN). */
+#define F71872_FDC	0x00	/* Floppy */
+#define F71872_SP1	0x01	/* UART1 */
+#define F71872_SP2	0x02	/* UART2 */
+#define F71872_PP	0x03	/* Parallel Port */
+#define F71872_HWM	0x04	/* Hardware Monitor */
+#define F71872_KBC	0x05	/* Keyboard/Mouse */
+#define F71872_GPIO	0x06	/* GPIO */
+#define F71872_VID	0x07	/* VID */
+#define F71872_PM	0x0a	/* ACPI/PME */
+
+#endif
diff --git a/src/superio/fintek/f71872/f71872_early_serial.c b/src/superio/fintek/f71872/f71872_early_serial.c
new file mode 100644
index 0000000000..474917a400
--- /dev/null
+++ b/src/superio/fintek/f71872/f71872_early_serial.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */
+
+#include <arch/romcc_io.h>
+#include "f71872.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0x87, port);
+	outb(0x87, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0xaa, port);
+}
+
+static void f71872_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c
new file mode 100644
index 0000000000..764dc541d3
--- /dev/null
+++ b/src/superio/fintek/f71872/superio.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "f71872.h"
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	outb(0x87, dev->path.pnp.port);
+	outb(0x87, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.pnp.port);
+}
+
+static void f71872_init(device_t dev)
+{
+	struct superio_fintek_f71872_config *conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	/* TODO: Might potentially need code for HWM or FDC etc. */
+	case F71872_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case F71872_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+	case F71872_KBC:
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	}
+}
+
+static void f71872_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void f71872_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void f71872_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	(dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
+	pnp_exit_conf_state(dev);
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = f71872_pnp_set_resources,
+	.enable_resources = f71872_pnp_enable_resources,
+	.enable           = f71872_pnp_enable,
+	.init             = f71872_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	/* TODO: Some of the 0x7f8 etc. values may not be correct. */
+	{ &ops, F71872_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, F71872_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, F71872_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+	{ &ops, F71872_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
+	{ &ops, F71872_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+	{ &ops, F71872_KBC,  PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0 }, },
+	{ &ops, F71872_GPIO, PNP_IRQ0, },
+	{ &ops, F71872_VID,  PNP_IO0, { 0x0ff8, 0 }, },
+	{ &ops, F71872_PM, },
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_fintek_f71872_ops = {
+	CHIP_NAME("Fintek F71872 Super I/O")
+	.enable_dev = enable_dev
+};