diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-15 19:35:14 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-15 19:35:14 +0000 |
| commit | a69d978be8a068944466e776de87527fb104a878 (patch) | |
| tree | 8acf4247e3104ad9ccb940568a81e472105a674b /src/superio/fintek/f71872 | |
| parent | 2e9323e5bef293c051d9fd982214e6db2e3305ee (diff) | |
C and other Super I/O cosmetic fixes.
- Random coding style, whitespace and cosmetic fixes.
- Consistently use the same spacing and 4-hexdigit port number format
in the pnp_dev_info[] arrays.
- Drop dead/unused code and less useful comments.
- Add missing "(C)" characters and copyright years.
- Shorten and simplify some code snippets.
- Use u8/u16/etc. everywhere.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/fintek/f71872')
| -rw-r--r-- | src/superio/fintek/f71872/superio.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 764dc541d3..f1a27e470d 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -92,15 +92,15 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x7f8 etc. values may not be correct. */ - { &ops, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, - { &ops, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0 }, }, + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71872_GPIO, PNP_IRQ0, }, - { &ops, F71872_VID, PNP_IO0, { 0x0ff8, 0 }, }, + { &ops, F71872_VID, PNP_IO0, {0x0ff8, 0}, }, { &ops, F71872_PM, }, }; |