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authorAngel Pons <th3fanbus@gmail.com>2020-03-16 23:17:32 +0100
committerMatt DeVillier <matt.devillier@gmail.com>2020-03-18 21:42:05 +0000
commit7c49cb8f9ca86e791c392da40e7f0d3cb7ed47f3 (patch)
treea9d37cd90987d0c5e17c7a5bb1c6380c7cda8eef /src/superio/fintek/f71869ad
parent1cd7d3e664fcf119a2b2f5e3fd8824b5682c6807 (diff)
nb/intel/sandybridge: Tidy up code and comments
- Reformat some lines of code - Move MCHBAR registers and documentation into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) With BUILD_TIMELESS=1, this commit does not change the result of: - Asus P8Z77-V LX2 with native raminit. - Asus P8Z77-M PRO with MRC raminit. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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