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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-20 10:49:38 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-26 07:09:24 +0200 |
| commit | 9551bed306aa54f5a707bde1d2a934a5341411b8 (patch) | |
| tree | b0196a18c38d2b2d193c1a00cda4db7294916908 /src/superio/common | |
| parent | d950f5191d1f7a0bd3a495cb630deda647d4245c (diff) | |
intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.
Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15761
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/superio/common')
0 files changed, 0 insertions, 0 deletions