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authorSubrata Banik <subrata.banik@intel.com>2021-01-29 18:41:35 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-02-01 08:55:34 +0000
commitcffc938934a9ee3b344ef594874e55f131bea77b (patch)
tree2cb88a28fe0b557fc772e0cc35cad547110cd292 /src/superio/aspeed
parent1cf2427d1d32b1055592213154eea9c31c287c2e (diff)
soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/aspeed')
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